Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Huawei Technologies Co., Limited

Future Wei Technologies, Inc.

Seagate Technology Incorporated

Pavel Anatolyevich Panteleev

Elyar Eldarovich Gasanov

Ilya Vladimirovich Neznanov

Andrey P Sokolov

Yurii Sergeevich Shutkin

Ivan Leonidovich Mazurenko

Pavel Aleksandrovich Aliseychik

Gleb Vyacheslavovich Kalachev

Aleksey Alexandrovich Letunovskiy

Alexander Andreev

Wen Tong

Carmela Cozzo

Andrey Nikitin

Alexandre Andreev

Earl T Cohen

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Jiang Li

Sergei B Gashkov

Oleg N Izyumin

Dmitriy Vladimirovich Alekseev

Ilya V Neznanov

Andre P Sokolov

Yuri Shutkin

A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.

Multi-label offset lifting method

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.

Method and apparatus for encoding and decoding LDPC codes

A base matrix of a rate-adaptive irregular QC-LDPC code is provided, the base matrix being formed by columns and rows having entries representing circulant submatrices. The columns of the base matrix are divided into at least one or more higher weight first columns and lower weight second columns and the rows of the base matrix are divided into first high weight rows corresponding to the high rate mother code and second low weight rows corresponding to the extension part related to the lower rate codes. A first submatrix formed by an intersection of entries of the second columns and entries of the first and the second rows is divided into first quadratic submatrices, wherein at most one entry in each column of each first submatrix and/or at most one entry in each row of each first submatrix is labelled.

Efficiently decodable QC-LDPC code

A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory.

Method for generating parity check matrix for low density parity check coding

An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.

Decoding based on randomized hard decisions

A receiver configured for use in a communication system, such as a magnetic recording channel, and having a soft-output channel detector provided with a soft-input/soft-output (SISO) modulation codec for parity bits of a block error-correction code. A transmitter of the communication system is configured to encode data by applying a modulation code to the parity bits that have been generated using the block error-correction code. The SISO modulation codec provides an interface between the soft-output channel detector and a parity-check decoder that enables decoding iterations between them in a manner that takes into account inter-bit correlations imposed by the modulation code. In some embodiments, the soft-output channel detector is configured to operate at a fractional rate and to process an input signal carrying non-binary symbols, and the parity-check decoder is configured to apply parity-check-based decoding that is based on a non-binary low-density parity-check code.

Apparatus for processing signals carrying modulation-encoded parity bits

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

Systems and methods for area efficient data encoding

A method of parallel decoding for a plurality of communications standards generally including steps (A) to (C) is disclosed. Step (A) may receive a plurality of first words, at least two of the first words generally have a different length than each other. Step (B) may parse the first words into a plurality of memories. Step (C) may generate a plurality of second words by decoding the first words using a plurality of decoders. The decoders generally operate in parallel. The decoding of at least one of the first words may be performed by at least two of the decoders. The decoding is generally based on a signal that identifies a current one of the communications standards used to transfer the first words.

Parallel decoder for multiple wireless standards

A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards

In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively large portions of input data.

Optimization of data processors with irregular patterns

A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher buffer level. A buffer module is configured to implement a packet queue that (i) enqueues received packets at the end of the queue in the order of their arrival to the buffer module, (ii) dequeues packets from the head of the queue, and (iii) advances packets toward the head of the queue when the buffer module transmits one or more packets to the higher buffer level or to a respective set of output ports connected to the buffer module.

Growing community of inventors

Moscow, Russia

Pavel Anatolyevich Panteleev