International Business Machines Corporation

Pavankrishna Ellore Ramesh

Silvia Melitta Mueller

Cedric Lichtenau

Jens Peter Seifert

Jörg-Stephan Vogt

Markus Lachenmayr

L'Emir Salim Chehab

Sourabh Chougule

A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.

Aligning most significant bits of different sized elements in comparison result vectors

The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

Method to build reconfigurable variable length comparators

Growing community of inventors

Hannover, Germany

Pavankrishna Ellore Ramesh