Intel Corporation

Pavan Kumar

Lilly Huang

Krishnan Ravichandran

Annabelle Pratt

Donald S Gardner

Harish Krishnamurthy

Wayne Proefrock

George Matthew

Sheldon Weng

Vivek K De

Robert A Dunstan

Eugene Gorbatov

Willem M Beltman

Tomm Aldridge

Vaibhav Vaidya

Jessica Gullbrand

Bradley Oraw

Karthik Sankaranarayanan

Horthense Delphine Tamdem

Donald R Alexander

Horacio Visairo-Cruz

Norma Bettine

Justin Tippetts

Horthense D Tamdem

Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module that is operably engaged with a platform. The memory module includes a non-volatile-memory block having a power supply controlled by the PMIC. The PMIC has a critical-fault signal pin that can be asserted to shut down the platform. The PMIC determines whether at least one critical fault occurred during a prior cycle, and also determines whether a critical fault occurs during a bootup sequence during a current cycle. Based on determining that a prior-cycle critical fault occurred and that a critical fault occurs during the bootup sequence, the PMIC sets a critical-fault indicator corresponding to the current critical fault; powers down the power supply; and does not assert the critical-fault signal pin.

Self-isolation of power-management integrated circuits of memory modules under fault conditions

Various embodiments comprise a protective circuit to connect at least two voltage rails to each other upon detection of the loss of the supply voltage that provides input power to the voltage regulators. The protective circuit may cause the two outputs of the voltage regulators to be connected to each other through a resistor when such a loss occurs. This in turn may prevent possible circuit damage in the load by preventing the higher output voltage from dropping below the lower output voltage if the capacitors on the outputs of the voltage regulators discharge at different rates. Such a reverse-voltage condition might otherwise cause damage in the load circuitry.

Maintaining proper voltage sequence during sudden power loss

In one embodiment of the invention, a low frequency converter is described that includes a first electrochemical capacitor to charge to an input voltage and a second electrochemical capacitor that is coupled to the first electrochemical capacitor. The second electrochemical capacitor is associated with an output voltage of the low frequency converter. Each electrochemical capacitor may have a capacitance of at least one millifarad (mF) and a switching frequency that is less than one kilohertz.

Low frequency converters having electrochemical capacitors

Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I. The difference between Vin and Vsw represents the maximum inductor current.

Digitally controlled zero voltage switching

One embodiment provides an apparatus. The apparatus includes a plurality of storage elements coupled in series. The storage elements are to capture and store energy received from a plurality of sources. The apparatus further includes a balancer coupled to the plurality of storage elements. The balancer is to balance energy drawn from each storage element.

Multisource power delivery system

Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

Low cost low overhead serial interface for power management and other ICs

Methods and apparatus relating to a single capacitor multi-phase three-level buck Voltage Regulator (VR) are described. In an embodiment, voltage regulator logic includes a first phase portion and a second phase portion. The voltage regulator logic also includes a single capacitor coupled between switches of the first phase portion and the second phase portion. Other embodiments are also disclosed and claimed.

Single capacitor multi-phase three-level buck voltage regulator

Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Techniques for reducing switching noise and improving transient response in voltage regulators

In one embodiment, the present invention includes a resilient power supply having a charger to charge a battery with a low voltage and to provide back-up battery power to a system; and a main power supply to provide a plurality of voltages for operation of the system. The resilient power supply may be used to discharge the battery into the main power supply upon loss of alternating current (AC) power in the system.

Providing resilient power to a system

A switched capacitor converter has a supply voltage input, an output circuit with one or more load capacitors, a semiconductor switch network. The switch network is connected at a switch junction point and across the voltage input, and has one or more pairs of said first and second switches. Each pair of switches is associated with one of the load capacitors and each pair is connected in series. The converter also has a charging capacitor network connected across the semiconductor switch network and across the voltage input. The charging capacitor network has one or more charging capacitors and inductances connected between the switch junction point and the output circuit. Each of the charging capacitors and inductances is associated with one of the load capacitors. The load capacitors are each charged by the associated charging capacitor when the associated first switch is closed and the associated second switch is open. And the load capacitors are each discharged by the associated inductance when the associated first switch is closed and the associated second switch is open.

Switched capacitor converters

In some embodiments, a three-switch dual output buck converter includes a converter circuit having N+1 switch circuits, the converter circuit being configured to receive an input voltage and to provide N output voltages, where N is two or more, and a control circuit to selectively provide control signals to the N+1 switch circuits at time intervals in accordance with the N output voltages, wherein the N output voltages include at least two different types of outputs. Other embodiments are disclosed and claimed.

Multiple output multiple topology voltage converter

An apparatus includes a plurality of output filters. Each output filter is to provide a respective output power signal at a respective voltage level. The apparatus also includes a plurality of power multiplexers. Each power multiplexer corresponds to a respective one of the output filters and each has a respective output coupled to an input of the respective one of the output filters. Each of the power multiplexers has a plurality of inputs. The apparatus further includes a plurality of power cells. Each power cell is coupled to a respective input of at least some of the power multiplexers. In addition, the apparatus includes a control unit to control the power multiplexers to selectively establish a connection between the output of each power multiplexer and at least one of the inputs of the power multiplexer.

Power distribution network for computer systems and other low-power applications

A method, apparatus, and system are described in which operating characteristics of voltage regulator (VR) may be controlled. Example operating characteristics that are controlled may be 1) power conversion efficiency based on load demand on the VR, 2) response rate to a transient deviation from a regulated output parameter, such as voltage or current, of the VR based on either 1) measured load or 2) receipt of an indication from a first load communicating that anticipated load conditions may cause the transient deviation from a set point of the regulated output parameter due to a significant change in load demand, or other similar operating characteristic. The VR may select an operating input voltage from two or more input voltages to control the operating characteristics of the VR by receiving a selection signal. Other embodiments are described.

Various methods and apparatuses for a multiple input-voltage-level voltage-regulator and a multiple voltage-level DC power supply

In some embodiments, a three-switch dual output buck converter includes a converter circuit having N+1 switch circuits, the converter circuit being configured to receive an input voltage and to provide N output voltages, where N is two or more, and a control circuit to selectively provide control signals to the N+1 switch circuits at time intervals in accordance with the N output voltages. Other embodiments are disclosed and claimed.

Growing community of inventors

Portland, OR, United States of America

Pavan Kumar