Raynet Corporation

Paulmer M Soderberg

William R Freeman

William R Apple

Mark S Thomas

Thomas E Giles

Ralph A Narciso

Lyle Thompson

Kristin K Foss

A coupler verification test circuit includes first and second circuits one of which is disposed at a head end of an optical fiber network and the other of which is disposed at a subscriber interface unit to be attached to the network when the head end is not operational. The subscriber interface circuit transmits instructions to a transceiver board in the subscriber interface unit for transmission to the network head end whereat the circuit thereat generates either no return signal, an acknowledgment return signal, or a default return signal. The test circuit at the subscriber interface unit then analyzes the return signal and visually indicates to a craftsman whether or not the transceiver board and other components of the SIU are operating correctly, e.g. whether or not the acknowledgement signal was returned and detected.

Coupler verification test circuit

A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

Clock recovery apparatus

A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.

Clock recovery apparatus including a clock frequency adjuster

Growing community of inventors

Menlo Park, CA, United States of America

Paulmer M Soderberg