Advanced Micro Devices Corporation

Pauling Chen

Binh Quang Le

Lee Edward Cleveland

Mark W Randolph

Darlene G Hamilton

Yi He

Edward Franklin Runnion

Zhizheng Liu

Ming-Huei Shieh

Edward Hsia

Michael Achter

Eric M Ajimine

Roger Tsao

A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltage

A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Pre-charge method for reading a non-volatile memory cell

An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array

Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage

A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

Selection circuit for accurate memory read operations

A memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.

Circuit for fast and accurate memory read operations

The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The mictocontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device

The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The microcontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

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Saratoga, CA, United States of America

Pauling Chen