Cadence Design Systems, Inc.

Paula Selegato Mathias

Habeeb Farah

Lars Lundgren

Björn Håkan Hjort

Tulio Paschoalin Leao

Artur Melo Mota Costa

Alberto Manuel Arias Drake

Guilherme Seminotti Braga

Ahmad S Abo Foul

Rodrigo Fonseca Rocha Soares

Gabriel Guedes De Azevedo Barbosa

Tales Bontempo Cunha

Eran Talmor

Rogério De Souza Moraes

A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version of the model of the electronic device and presenting as a status result for each the instantiations of a plurality of the properties of the current version of the model of the electronic design the preferred status result obtained for that instantiation of the property per the same unique signature value that was calculated for that instantiation of the property in previous runs of the plurality of formal verification regression runs.

Method and system for assertion-based formal verification using unique signature values

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.

Systems and methods for command interpretation in an electronic design automation environment

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Nova Lima, Brazil

Paula Selegato Mathias