California Institute of Technology

Other

Paula J Grunthaner

Frank J Grunthaner

Michael E Hoenk

True-Lon Lin

Charles E Bryson, Iii

Michael H Hecht

Robert W Fathauer

Robert W Terhune

A vacuum window transmitting keV electrons and usable for high-pressure electron analysis such as XPS and AES in which the sample is positioned outside the UHV analyzer chamber, possibly in a controlled gas environment, relatively close to the window. The window includes a grid formed from a support layer and a thin window layer supported between the ribs and having a thickness preferably of 2 to 3 nm. The window and support layers may be deposited on a silicon wafer and the support layer is lithographically defined into the grid. The wafer is backside etched to expose the back of the grid and its supported window layer. Such a window enables compact and easily used electron analyzers and further allows control of the gas environment at the sample surface during analysis.

Electron transmissive window usable with high pressure electron spectrometry

The backside surface potential well of a backside-illuminated CCD is confined to within about half a nanometer of the surface by using molecular beam epitaxy (MBE) to grow a delta-doped silicon layer on the back surface. Delta-doping in an MBE process is achieved by temporarily interrupting the evaporated silicon source during MBE growth without interrupting the evaporated p+ dopant source (e.g., boron). This produces an extremely sharp dopant profile in which the dopant is confined to only a few atomic layers, creating an electric field high enough to confine the backside surface potential well to within half a nanometer of the surface. Because the probability of UV-generated electrons being trapped by such a narrow potential well is low, the internal quantum efficiency of the CCD is nearly 100% throughout the UV wavelength range. Furthermore, the quantum efficiency is quite stable.

Growth of delta-doped layers on silicon CCD/S for enhanced ultraviolet

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Silicon sample holder for molecular beam epitaxy on pre-fabricated

Pinhole-free epitaxial CoSi.sub.2 films (14') are fabricated on (111)-oriented silicon substrates (10) with a modified solid phase epitaxy technique which utilizes (1) room temperature stoichiometric (1:2) codeposition of Co and Si followed by (2) room temperature deposition of an amorphous silicon capping layer (16), and (3) in situ annealing at a temperature ranging from about 500.degree. to 750.degree. C.

Growing community of inventors

Glendale, CA, United States of America

Paula J Grunthaner