Fujitsu Corporation

Rambus Inc.

Paul Wong

Kevin D Jones

Qiang Hong

Thomas J Sheffler

Kathryn M Mossawir

Jing Jiang

Dwight K Elvey

Mark O Porter

Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.

Method to analyze an analog circuit design with a verification program

A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.

Multi-format consistency checking tool

A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.

Mixed mode verifier

The present invention relates to an improved digital circuit design employing scannable state elements. In one embodiment, a digital circuit design includes a first functional latch coupled to a first logic block and a second functional latch coupled to a second logic block. The functional latches are in separate scan chains and receive their own respective scan in inputs. The functional latches are both coupled to a common holding latch that captures content from the functional latches. In another embodiment, the digital circuit design includes two logic blocks that are coupled to a scannable state element. The functional latch is disposed within two different scan chains and receives scan in inputs from both scan chains. The functional latch may test the first and second logic blocks to provide controllability and observability. By sharing a common scannable state element, the invention reduces overhead and space in the circuit design.

Scannable state element architecture for digital circuits

An apparatus for obtaining valid values during a built-in self-testing of logic (&ldquo;LBIST&rdquo;) is disclosed. The apparatus includes a first multiplexer, a second multiplexer and a 1-hot init circuit. The 1-hot init circuit includes a scan register, a first inverter, a third multiplexer, a second inverter, and a fourth multiplexer. The scan register includes a plurality of state elements. The first multiplexer is coupled to receive a random data signal and an output of the 1-hot init circuit. Within the 1-hot init circuit, a next to last and a last state element of the scan register is coupled to the inverters and the third and fourth multiplexers, respectively. The first inverter is also coupled to the third multiplexer and the second inverter is coupled to the fourth multiplexer. The output of the fourth multiplexer is coupled to the input of the second multiplexer. Also coupled to the input of the second multiplexer is an input for the random data signal. The output for the second multiplexer is coupled to a signature compression circuit. Also disclosed is a method for flushing the state elements in the 1-hot init circuit for receiving a 1-hot value after flush. Also disclosed is a method for ensuring values that a 1-hot multiplexer selects are orthogonal and that inputs to a signature compression circuit are valid.

Handling a 1-hot multiplexer during built-in self-testing of logic

The initialization process and structure of the system ensure that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the state elements in scan chains that cannot tolerate random data. A scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a &ldquo;LBIST Non-random Scan Chain&rdquo; (LNSC). A PRPG generates random data having a plurality of bit values to the LRSCs which is then passed to a multiple input shift register (MISR). The LNSCs do not receive random data from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and the LNSCs feed bit values reflecting test responses into the MISR. The system may further include recirculation lines in electrical communication with a LNSC to recirculate original bit values back into the LNSC.

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San Jose, CA, United States of America

Paul Wong