International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Paul Wingshing Chung

Stephen A Jove

John Thomas Contreras

Paik Saber

Klaas Berend Klaassen

John E Gersbach

Kevin Roy Vannorsdel

Calvin Shizuo Nomura

Niantsu N Wang

Karl R Hense

Richard Edward Matick

Michael O Jenkins

David A Freitas

Ramesh C Varshney

Jacobus C Van Peppen

Bac V Pham

Jacobus Cornelis Leonardus Van Peppen

Daniel T Ling

Ralph L Gee

David S Lowrie

Eugene M Blaser

Kim Y Nguyen

John Thomas Conteras

Chorng K Wang

Luke C Lang

Pete Granata

A method and apparatus for providing quadrature biasing for coupled-pair circuits. A QBCP-circuit for quadrature amplifiers provides a new input common-mode sense point that separates the inputs for the differential-and-common mode feedback-control loops. The QBCP circuit biases all four transistors equivalently and reduces the feedback-loop interaction, thereby simplifying the bias control system and improves the voltage-transfer frequency-response performance.

Method and apparatus for providing quadrature biasing for coupled-pair circuits

Bi-Variant Coupled Pair (BVCP) circuits suitable for use in channel front-end low noise preamplifiers of magnetic storage devices are described. In a magnetic storage device, a BVCP circuit provides a DC bias voltage for a read transducer, low-noise amplification performance, and relatively small AC coupling capacitor values for reducing the cost of an integrated circuit (IC) in which the BVCP circuit may be embodied. The BVCP circuit also has a controllable input impedance for matching a transmission line impedance for high data rate applications.

Preamplifier circuit suitable for use in magnetic storage devices

A method and apparatus for high voltage applications, with the latest MOSFET technology having limited terminal-to-terminal voltage capability, includes a switch circuit having at least two serially coupled MOSFETs and a two-stage MOSFET connection using a plurality of resistors, and/or a bipolar transistor, and a plurality of diodes. One of the high voltage applications is a high speed write driver in a computer disk drive. The switch circuit switches on/off between zero volt and a voltage higher than a maximum terminal-to-terminal voltage of a single MOSFET which is typically five volts. A required voltage in high voltage applications can be in excess of, for example, 8 or 9 volts.

Method and circuitry for high voltage application with MOSFET technology

A method and system for providing a current-sensing preamplifier for use with a magnetoresistive sensor is disclosed. The method includes providing at least one input device coupled with the magnetoresistive sensor, providing a gain stage, and providing a feedback circuit. In a system aspect, the current-sensing preamplifier includes at least one input device. The at least one input device is coupled with the magnetoresistive sensor through an interconnect having a characteristic impedance. The at least one input device provides an input impedance for the current-sensing preamplifier. The current-sensing preamplifier also includes a gain stage coupled with the at least one input device and a feedback circuit coupled with the gain stage and the at least one input device. The feedback circuit provides at least one signal to the at least one input device. The at least one signal controls the input impedance based on at least one error signal.

Quasi-current sensing input impedance controlled preamplifier for magnetoresistive elements

An accurate current source with an adjustable temperature dependence. This type of current source is used in silicon Integrated Circuit (IC) designs requiring supporting reference-voltage sources and/or reference-current sources which may be designed with or without temperature dependence. The circuit generates an accurate current with temperature independence along with another accurate current source with temperature dependence using only one precision external resistors. For the temperature-dependent current source, the temperature dependence can be controlled by setting a temperature dependence factor (TDF).

Accurate current source with an adjustable temperature dependence circuit

A multi-state preamplifier having a first detector and a second detector provides voltage-sensing and current-sensing signal amplification, respectively. Either the first detector or the second detector is selected and switched active at any given time, producing an amplified signal representing either the signal voltage developed across the MR element or the signal current flowing through the MR element, respectively. The switching process to activate either the first detector or the second detector is carried out by a detector determining circuit connected to a disk drive control unit. The detector giving the optimum high frequency bandwidth for the preamplifier is chosen based on the resistance of the MR element coupled with the input interconnect network characteristic and parasitic impedances.

Multi-state preamplifier for disk drives

A method and system for providing a voltage-sensing preamplifier for use with a magnetoresistive sensor is disclosed. The method includes providing a gain stage and providing a control circuit. The system includes the gain stage and the control circuit. The gain stage includes at least one input device that is coupled with the magnetoresistive sensor through an interconnect having a characteristic impedance. The at least one input device has a first input impedance. The control circuit provides at least one signal to the at least one input device. The at least one signal controls the first input impedance of the at least one input device to control a second input impedance of the voltage-sensing preamplifier, such that the preamplifier input impedance is modified toward the characteristic impedance of the interconnect to improve the bandwidth of the signal amplified by the system.

Quasi-voltage sensing input impedance controlled preamplifier for magnetoresistive elements

The present invention is a preampifier circuit for magnetoresistive (MR) elements which has a high imput impedance with respect to the MR resistance so that the resultant system would not be sensitive to the series input inductance of the leads necessary to connect the MR element with the preamplifier. With former preamplifiers, nearly all are low impedance types, (using either BiCMOS or BiPolar technology), or differential (using BiPolar technology). The present invention fills a need in the prior art by providing a preamplifier curcuit using BiCMOS technology with a high input impedance, and single ended (SE) topology for minimum power dissipation.

High input impedance single ended, low supply voltage magnetoresistive preamplifier circuits

A method and apparatus for re-initializing a GMR head after losing initialization is disclosed. The invention may use a voltage controlled waveform, which allows the current to vary with the resistance of the GMR head. Furthermore, according to a further aspect of the invention a stack of GMR heads may be reinitialized having the same orientation to preclude inversion of the reset magnetic fields on half of the heads. In addition, improvements in re-initializing GMR heads is provided by implementing wave shaping. The invention can also provide re-initialization of GMR heads at different points in the manufacturing process.

Preamplifier bias mode to re-initialize a GMR head after losing

An FET write driver providing high rates of data transfer to a magnetic storage medium by effectively utilizing the voltage swing provided by supply voltage. A first and a second p-channel FET power switch are coupled between the voltage supply and the inductive head, each having a high aspect ratio for low resistance. A first and a second current mirror are coupled at their inputs to the inductive head and a current source, each current mirror having a reference arm coupled to the current source and a mirror arm coupled to the inductive head. Each current mirror has an output coupled respectively to a first and a second mirror enabling FET switch, each having a high aspect ratio for low resistance. A pair of differential signals dp and dn selects the ON and OFF states of the FET switches to provide either a first current path through the first FET power switch and the second current mirror to provide a write current in a first direction or a second current path through the second FET power switch and the first current mirror to provide a write current in a second opposite direction. During operation, the low voltage drops across the FET switches allow for a substantial portion of the voltage supply to be available for writing using the inductive head. The circuit is inherently stable and avoids ringing and overshoot, which results in improved timing and maintains signal integrity. The write driver can operate with low voltage power supplies for cost reduction or low power consumption in products such as portable computers while still retaining a high data transfer rate. For multiple head disk drive units, a plurality of write drivers are provided that include an additional switch at the current source input, which allows a single current source to be utilized as a reference current and a single set of differential signals to control all of the write circuits.

High speed FET write driver for an inductive head

An analog receiver circuit suitable for use with a flash analog-to-digital converter is described. A first stage of the receiver acts essentially as a voltage follower, receiving the centertap voltage of a flash A/D converter resistor ladder, and maintaining an internal reference voltage substantially equal to the centertap voltage over time. A second stage of the analog receiver acts as centering means, receiving an analog signal and centering it with respect to the internal reference voltage provided by the first stage. The receiver is thus able to provide an analog signal to the flash A/D converter which is dynamically centered with respect to the converter's operating voltage, thereby reducing DC offset. Moreover, introducing the analog signal at the second stage minimizes the bandwidth-limiting elements between this input signal and the DC-centered output signal. Thus DC offset is further reduced and operating frequencies of 500 MTz or greater are possible.

DC centering analog receiver for flash A/D converter

An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no additionally introduced delay. The circuit includes an imbalancing element which is coupled to a latching portion of the circuit. The latching portion of the circuit comprises a pair of cross-coupled transistors, in current mode embodiments of the invention, or a pair of cross-coupled inverters, in voltage mode embodiments of the invention. The imbalancing element introduces an electrical disturbance on the input line to one of the latching transistors or inverters. The imbalancing element is a capacitor in voltage mode embodiments of the invention and an additional transistor in current mode embodiments.

Assertive latching flip-flop

A method and circuitry for suppressing additive transient disturbances in an analog differential input signal, such disturbances being due, for example, to thermal asperity transients caused by an MR transducer contacting a moving storage surface. The input data signal is algebraically summed with a corrective feedback signal for providing as output signal. The output signal is fed back to a circuit including an envelope detector and differentiator and converted into another signal that is the derivative of an amplitude envelope corresponding to the output signal. Nonlinear signal-adaptive filter means converts said other signal into the corrective feedback signal, which substantially replicates the additive transient disturbance and is subtracted from the data input signal to render the output signal substantially free of the transient disturbance. The input, output and corrective signals are preferably differential signals.

Method and circuitry to suppress additive disturbances in data channels

A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

BiCMOS analog-to-digital converter with minimized metastability

A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

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San Jose, CA, United States of America

Paul Wingshing Chung