3com Corporation

Affirmed Networks, Inc.

U.S. Ethernet Innovations, LLC

3 Com Corporation

Paul William Sherer

Glenn William Connery

Richard S Reid

Niles E Strohl

James P Rivers

Richard J Hausman

Cynthia Zikmund

Anand Krishnamurthy

Srinivasan Venkatraman

Hassan Ahmed

Jae Won Chung

Peter Si-Sheng Wang

Deepak Garg

Terry Durand

Kenneth Araujo

Tim Mortsolf

Avnish Sikka

Methods of and systems for packet gateway and content management integration are disclosed. An integrated gateway and content management module provides content to mobile user equipment from a content delivery network. The module operates on the content based on information about the mobile user equipment and/or network entities with which the mobile user equipment is communicating and information about the content being provided. The integrated gateway and content management module discovers said information.

Method of and system for packet gateway and content management integration

Methods and apparatus, including computer program products, for mobile video delivery. A method includes, in a mobile network comprising at least a core element and one or more evolved Node Bs (eNBs), receiving a request to initiate a progressive download of a video object, splitting the requested video object into self-contained independent video segments, transrating each of the self-contained independent video segments for different rates, and delivering a segment from a rate bucket that matches a current network condition determined by bandwidth estimation.

Mobile video delivery

Methods and apparatus, including computer program products, for aggregating multiple functions into a single platform. A communications system includes at least one processor, at least one computer readable storage medium storing computer executable instructions that, when executed by the at least one processor, implement components including a workflow module comprising sets of workflow instructions for processing different types of information packets, and selectable communication function modules, the workflow module coordinating processing of a received packet using selected ones of the selectable communication function modules.

Aggregating multiple functions into a single platform

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating data transfer

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

A communications network system that transmits and receives communication frames that include a transmission status section that indicates a communication frame transmission is aborted. In one embodiment, a transmission status section includes a cyclical redundancy check value that is non-matching with the information in the communication frame. For example, a non-matching cyclical redundancy check value is created by generating a one's compliment of a CRC calculated based upon the information within a communication frame. The communication network includes a wireless network, a wired network (e.g., an Ethernet network) and a data cable system that transmits a data over cable media access control (MAC) frame with an Ethernet/&lsqb;ISO8802-3&rsqb; type packet protocol data unit payload.

Method and system to abort data communication traffic in a communication network

Programmed I/O ethernet adapter with early interrupt and DMA control for

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating

Apparatus for simulating a stack structure using a single register and a

In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.

Growing community of inventors

Sunnyvale, CA, United States of America

Paul William Sherer