Texas Instruments Corporation

Paul William Krause

Karl Friedrich Greb

Kevin Patrick Lavery

Alexandre Pierre Palus

Yanyang Xiao

Sridhar Vajapey

John M Bach

An electronic circuit includes a microcontroller processor (), a peripheral () coupled with the processor, an endian circuit () coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit () to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Endian configuration memory and ECC protecting processor endianess mode circuit

Encode and multiplex, register, and decode and error correction circuitry

In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits are arranged in a packing order. Next, all the forcing bits are set to a logical zero value. A first error correction term is generated using the data field and forcing bits as an input to an ECC encoding algorithm. An exclusive OR function is performed on the constant error correction term and the first error correction term creating a difference term. A forcing function is applied to the difference term creating a new value for the forcing bits. The data field and the forcing bits are written to the flash memory.

Progressively programming flash memory while maintaining constant error correction codes

A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input exclusive not OR circuit and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output signal, and at least one second register cell having a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input exclusive not OR circuit having a first input connected to said seventh output signal of said second input multiplexer and a second input connected to a cell output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal of said second input exclusive not OR circuit and having a second cell output signal.

Multifunction register

Growing community of inventors

Sugar Land, TX, United States of America

Paul William Krause