Nxp B.v.

Paul Wielage

Dominique Delbecq

Richard P Kleihorst

Fred Mostert

Alexander Alexandrovich Danilin

Martinus Theodorus Bennebroek

Mohamed Azimane

Gertjan Van Holland

Mathias Martinus Van Ansem

Jose De Jesus Pineda De Gyvez

Hamed Fatemi

Ayoub Rifai

A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.

System and method of digital to analog conversion using dynamic element matching

A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

Processor having a register file, processing unit, and instruction sequencer, and operable with an instruction set having variable length instructions and a table that maps opcodes to register file addresses

A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.

Load detector

A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

SIMD parallel processor architecture

An asynchronous ripple pipeline has a plurality of stages, each with a controller () and a register (). The controller has a register control output (), and a combined acknowledgement and request output (), together with a request input () and an acknowledgement input (). The protocol used has a single signal, output on the combined acknowledgement and request output () of a stage (), that functions both as a request to the next stage () and an acknowledgement to the previous stage ().

Asynchronous ripple pipeline

A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.

Method for testing a static random access memory

A circuit has a plurality of functional circuits (-), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (-) comprises a chain of one-shot circuits (-), each comprising a bi-stable circuit (). The bi-stable circuit () of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (), the bi-stable circuits () of a remaining or each remaining one-shot circuit (-) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit () has an output coupled to a respective one of the multiphase control outputs (-) and a reset input coupled to the respective one of the multiphase control outputs (-). Loading of the multiphase control outputs (-) by the functional circuits results in a delay of the reset. Thus the pulse durations of the one shot circuits are adapted to the number of functional circuits to ensure sufficient signal development.

Growing community of inventors

Waalre, Netherlands

Paul Wielage