Siemens Aktiengesellschaft

Infineon Technologies Ag

Micronas Gmbh

Paul-Werner Von Basse

Roland Thewes

Michael Bollu

Doris Schmitt-Landsiedel

Josef Willer

Emmerich Bertagnolli

Franz Hofmann

Reinhard J Stengl

Thomas Scheiter

Ruediger Hofmann

Stephan Marksteiner

Bernd Goebel

Jean-Marc Dortu

Ulrich Schaper

Barbara Hasler

Heinz Opolka

Dieter Kohlert

Andrea Herlitzek

Thorsten Sasse

Wolfgang Krautschneider

Hans Reisinger

Domagoj Siprak

Christian Peters

Michael Melzl

Reinhard Fischbach

Ute Kollmer

Rudiger Hofmann

Andreas Luck, Deceased

Doris Schmitt-Lansiedel

Rainer Grossmann

Andreas Gaymann

Thomas Rosteck

Reinhard G&ouml;llner

Klaus Hammer

Markus Witte

Siegfried Röhl

Justin Bierner

By Inge Booken, Legal Representative

By Manfred Luck, Legal Representative

A circuit and method are provided for ensuring that a fingerprint sensor is started automatically when a finger is rested thereon such that a sufficiently contrasting image can be produced. A difference between a maximum and a minimum value of the sensor signals is generated wherein, if the difference is sufficiently large, indicating a sufficient contrast of an image to be produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint image is produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint images produced are of satisfactory quality.

Circuit arrangement and method for operating a fingerprint sensor

A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.

Passivation layer structure

An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric layer, and an electrically conductive guard structure. The guard structure is disposed in a plane above the conductive surfaces such that the conductive surfaces are not completely covered by the guard structure.

Electronic component and utilization of a guard structure contained therein

A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials

A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.

Method of determining very small capacitances

A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

Method for capacitive image acquisition

The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G,G,G,). Parts of the memory cell such as, for example, gate electrodes (Ga,Ga,) or conductive structures (L,) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H,) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L,) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D,) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B,) or/and via conductive structures (L,L,, L,) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K,) contact a plurality of parts of the MOS transistors simultaneously.

SRAM cell arrangement and method for manufacturing same

An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.

Steep edge time-delay relay

Method for the manufacturing a memory cell configuration

Device for the jump-like addressing of specific lines of a serially

In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ('1,' '0') differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

Pointer circuit with low surface requirement high speed and low power

Memory cells are organized in cell fields in word lines and bit lines in the manner of a matrix. The bit lines are actuated by a bit decoder for loading with a mass potential, and by a blocking decoder for loading the bit lines with a blocking potential. The word lines are actuated by a word decoder for loading the word lines with a programming voltage or a protective voltage. The information value to be programmed is prestored in the cell field.

Method for programming a ROM cell arrangement

A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information '0' are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.

Matrix memory in virtual ground architecture

The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).

Memory cell arrangement of memory cells arranged in the form of a matrix

Growing community of inventors

Wolfratshausen, Germany

Paul-Werner Von Basse