Infineon Technologies Ag

Qimonda Ag

Paul Wallner

Peter Gregorius

Christian Sichert

Hermann Ruckerbauer

Dominique Savignac

Martin Streibl

Dieter Metzner

Thomas Rickes

Yukio Fukuzo

Thomas Hein

Manfred Menke

Ralf Schledz

Peter Widerin

Chaitanya Dudha

Stefan Dietrich

Daniel Kehrer

Andre Schaefer

Edoardo Prete

Tim Schoenauer

Andre Schäfer

Abdallah Bacha

Paul Schmölz

Masthan Devalla

In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.

Receiver architecture

In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.

An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Over-current detection for bus line drivers

An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Shutdown protection for bus line drivers

In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from a read data input interface to be re-driven to the next memory chip.

Semiconductor memory chip and memory system

A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.

Refreshing the content of a memory cell of a memory arrangement

A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

Memory arrangement having efficient arrangement of devices

A memory device including a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

Memory device, memory system and method of operating such

A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

Memory device and method of operating such

Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

Method of transferring signals between a memory device and a memory controller

A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.

Memory arrangement

A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

Semiconductor memory system and semiconductor memory chip

A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

Data conversion

In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.

High-speed interface circuit for semiconductor memory chips and memory system including the same

A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

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Prien, Germany

Paul Wallner