Motorola Corporation

Freescale Semiconductor,inc.

Adeia Semiconductor Bonding Technologies Inc.

Nxp Usa, Inc.

Freescale Semiconductors Inc.

Paul W Sanders

Michael F Petras

Chandrasekaram Ramiah

Robert E Jones

Thuy B Dao

Bernard W Boland

Joel E Keys

Robert A Pryor

Xiaowei Ren

Wayne R Burger

Douglas G Mitchell

Robert J Johnsen

Robert Bruce Davies

Stephen P Robb

Julio C Costa

Hernan A Rueda

John L Freeman, Jr

Scott L Craft

Randy L Pollock

Alan D Wood

Charles T Lambson

Troy E Mackie

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Monolithic microwave integrated circuits

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Methods of forming 3-D circuits with integrated passive devices

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face () of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Methods of making a monolithic microwave integrated circuit

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates () and lower resistance inductors (') for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--&#x2033;) overlying the substrate (). The active transistor(s) (&#x2032;) are formed in the substrate () proximate the front face (). Planar capacitors (&#x2032;) are also formed over the front face () of the substrate (). Various terminals (------&#x2032;, etc.) of the transistor(s) (&#x2032;), capacitor(s) (&#x2032;) and inductor(s) (&#x2032;) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (&#x2032;) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (&#x2032;) and heavy current carrying conductors (-&#x2032;) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

Monolithic microwave integrated circuit

A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Semiconductor structure having a through substrate via (TSV) and method for forming

3-D ICs () with integrated passive devices (IPDs) () having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates () coupled by through-substrate-vias (TSVs) (). An active device (AD) substrate () has contacts on its upper portion (). An isolator substrate () is bonded to the AD substrate () so that TSVs () in the isolator substrate () are coupled to the contacts () on the AD substrate (), and desirably has an interconnect zone () on its upper surface. An IPD substrate () is bonded to the isolator substrate () so that TSVs () therein are coupled to the interconnect zone () on the isolator substrate () and/or TSVs () therein. The IPDs () are formed on its upper surface and coupled by TSVs () in the IPD () and isolator () substrates to devices () in the AD substrate (). The isolator substrate () provides superior IPD () to AD () cross-talk attenuation while permitting each substrate () to have small high aspect ratio TSVs (), facilitating high circuit packing density and efficient manufacturing.

3-D circuits with integrated passive devices

Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about &#x2266;40, usefully &#x2266;10 and preferably &#x2266;5.

Through substrate VIAS

Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods

Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region () of a first thickness () proximate the front surface () of a substrate wafer () by: (i) from the front surface (), forming comparatively shallow vias () of a first aspect ratio containing first conductors () extending preferably through the first thickness () but not through the initial wafer () thickness (), (ii) removing material (&#x2033;) from the rear surface () to form a modified wafer () of smaller final thickness () with a new rear surface (), and (iii) forming from the new rear surface (), much deeper vias () of second aspect ratios beneath the device region () with second conductors () therein contacting the first conductors (), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about &#x2266;40, usefully &#x2266;10 and preferably &#x2266;5.

Through substrate vias

Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming () desired device regions () with contacts () on the front surface () of an initially relatively thick wafer ('); etching () via cavities () partly through the wafer (&#x2032;) in the desired locations; filling () the via cavities () with a conductive material () coupled to some device region contacts (); mounting () the wafer (&#x2032;) with its front side () facing a support structure (); thinning () the wafer (&#x2032;) from the back side () to expose internal ends (, etc.) of the conductive material filled vias (, etc.); applying () any desired back-side interconnect region () coupled to the exposed ends (, etc.) of the filled vias; removing () the support structure () and separating the individual device or IC assemblies () so as to be available for mounting () on a further circuit board, tape or larger circuit ().

Through substrate vias for back-side interconnections on very thin semiconductor wafers

A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Semiconductor through silicon vias of variable size and method of formation

A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

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Paul W Sanders