Cadence Design Systems, Inc.

Paul W Kollaritsch

Oleg Levitsky

Ping-Chih Wu

Harpreet Singh Anand

Mohan Kumar Chalamalashatty

Lokeswara R Korlipara

The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.

Generating a power grid for an integrated circuit

The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain additional aspects, embodiments include a power grid optimizer for optimizing portions of a power grid based on analytics such as QOR analytics, and incrementally updating the power grid to include these optimized portions.

Optimizing a power grid for an integrated circuit

Methods and systems for implementing prototyping and floorplanning for electronic circuit designs are disclosed. The method identifies or generates a representation of a design, modifies or updates the representation by moving a circuit component in the representation. The representation may be characterized in the pre-placement or post-placement stage to determine or identify distance constraints constraining object pairs in the representation. The method performs a timing and/or congestion analysis with distance-based timing information having a spatial dimension rather than timing information having a temporal dimension for the representation of the electronic design. The timing and/or congestion analysis is performed during the circuit component is being moved or shortly after the circuit component has been moved. The results of the timing and/or congestion analysis are provided in an interactive manner or in a batch mode.

Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs

Disclosed is an improved method, system, and computer program product for implementing flexible models to perform efficient prototyping of clock structures in electronic designs, which allows for very efficient analysis of the electronic designs. Some approaches pertain to usage of the flexible abstraction models that also include clock abstractions to more efficiently perform analysis upon the electronic designs. This allows greater analysis efficiency with regards to timing analysis and physical analysis.

Method and system for implementing clock tree prototyping

Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.

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Solana Beach, CA, United States of America

Paul W Kollaritsch