Quantum Corporation

Digital Equipment Corporation

Paul W Kemp

Donald W Smelser

Charles F Cassidy

Richard A Rudman

Anh T Tran

A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly 'perfect.' A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. In a addition the computer system includes a solid-state disk type memory for a computer system is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is employed to perform a Reed-Solomon code type of error detection and correction. A primary feature is the recognition that it is no longer necessary that all DRAM devices be ostensibly 'perfect.' A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. A preferred data formatter circuit to convert between symbol and word data is also described.

Solid state disk memory using storage devices with defects

A fault detection arrangement provides error detection and verification of generated address sequences for the execution of read/write operations in a storage subsystem. The arrangement also prevents corruption of data stored on the subsystem array module. Gray code counters located in the address path of the array module generate sequential addresses and associated parity for words of a block of data, based on a starting address received from a storage controller. As each address is generated and transferred to storage devices of the array, a parity checker regenerates parity information associated with the transferred address and compares that parity information to the parity information received from the counters. If an address error is detected, execution of the read/write operation is suppressed and the controller is immediately notified of the error.

Address error detection technique for increasing the reliability of a

A fault tolerant addressing arrangement for a solid-state disk comprising partially defective memory devices is provided. The addressing technique increments both row and column addresses when establishing locations for the storage of symbols so that the same rows and columns are not addressed for any two symbols. The technique also complements certain portions of the symbols' address to ensure addressing of different locations within each memory device.

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Northborough, MA, United States of America

Paul W Kemp