Ati International Srl

Other

Advanced Micro Devices Corporation

Chromatic Research, Inc.

Paul W Campbell

Korbin S Van Dyke

Stephen C Purcell

Don A Van Dyke

Ali Alasti

Shalesh Thusoo

Ronak Patel

Sanjay Mansingh

T R Ramesh

Gurjeet Singh Saund

Tr Ramesh

Alan McNaughton

An illustrated side view of an exemplary medication for treating ulcerative colitis is presented. The medication is useful for reducing the risk and debilitation associated with having ulcerative colitis, as well as improving overall health. The medication further is useful for removing life threatening complications such as, but not limited to, perforated colon, liver disease, inflammation of skin, joints and eyes, decreasing the risk of colon cancer while eliminating the need for surgery for relief of the ulcerative colitis. The medication is also inexpensive and all natural.

Ulcerative colitis medication

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Method and apparatus for dynamic allocation of processing resources

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.

Managing instruction side-effects

A retaining-locking system for chain link fence slats includes specially notched fence slat elements having a pointed upper or lower end. The slat elements are sized and shaped to be interwoven between consecutive links of a chain link fence. A retaining-locking strip is formed of resilient material, and has an inner surface and an outer surface and at least one securing protrusion. The securing protrusion is sized and shaped to fit slidably within the notch. The protrusion is located on the outer surface of the strip. When the slat elements are interwoven into between consecutive links of a chain link fence with each of the notches aligned with one another, the retaining-locking strip inserted between the slat elements and the links, with the securing protrusion disposed within the slats, the strip will urge the slats toward the links, thereby retaining the slats within the chain link fence.

Retaining-locking system for chain link fence slats

A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set. The CISC instruction set provides accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set.

Computer for execution of RISC and CISC instruction sets

A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.

Exception mechanism for a computer

A method and apparatus for virtual address translation include processing that begins by receiving a memory access request that includes a virtual address. The processing continues by determining whether a physical address translation has been performed for the virtual address. Note that a physical address translation translates the virtual address into an address. The address either corresponds to physical address of memory or is further translated into another physical address of memory. The processing continues when the address, which resulted from the physical address translation or the another physical address translation, is stored in a translation look aside table (TLB). When the physical address translation or the another physical address translation has not been performed, the processing retrieves a physical page address based on a portion of the virtual address. The processing continues by determining whether the physical page address corresponds to a physical address requiring further translation (e.g., is within the AGP window). If not, the physical page address and a portion of the virtual address are used to produce the physical address. If the address is within the physical address requiring further translation, a second physical page address is retrieved. Utilizing the second physical page address and a portion of the virtual address, another physical address is produced. Both the translations (i.e., the physical address and the another physical address) are stored within the same TLB of the central processing unit.

Method and apparatus for virtual address translation

A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page table entry has not been asserted. If the accessed bit is not asserted, an electrical circuit causes an accessed bit exception and branches execution to a second software exception handler. The second software exception handler asserts the accessed bit in the page table entry in main memory. The second software exception handler returns control back to the original memory access, causing execution to resume where it had left off prior to the TLB miss exception. This process may be practiced for an upper-level page table entry or a lower level page table entry.

Method and apparatus for handling an accessed bit in a page table entry

A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Method and apparatus for cache memory management

A method and apparatus is provided for providing communication with input/output devices without being bound by the limitations of an existing input/output bus while still providing compatibility with software intended to communicate with input/output devices using the existing input/output bus. The software image of the input/output devices as being associated with the input/output bus is preserved, but a technique is provided to allow communication with the input/output devices to bypass the existing input/output bus. A translation lookaside buffer is utilized to remap accesses to an internal input/output device from virtual address space for input/output-bus-based input/output devices to physical address space for the internal input/output device. Circuitry for interfacing with the input/output devices separately from the existing input/output bus may be fabricated as a single integrated circuit device along with other system components, such as a central processing unit.

Allocation of input/output bus address space to native input/output devices

A method and apparatus for generating a specific computer hardware component exception handler and emulating memory accesses to such a hardware component include processing steps that begin by determining whether an address of a CPU instruction is within the address space of the computer hardware component. When the address is within the address space of the computer hardware component, the address and data size are saved in emulation registers. The processing then continues by entering a software exception handler to process the memory access requests directed to the computer hardware component based on the data size. The processing within the software exception handler begins by reading from a plurality of computer hardware component registers to obtain a register setting. The processing then continues by generating a specific computer hardware component function based on the register settings. The processing then continues by storing the specific computer hardware component function in cache memory. The process then continues by performing the specific computer hardware component function upon data to produce a specific emulated hardware component data. The performance of the specific computer hardware component function may be done by executing an instruction that identifies an address and data size.

Method and apparatus for generating a specific computer hardware component exception handler

A method and apparatus for dependent segmentation and paging processing within a computer system include processing that begins by determining context of an operation supported by a native operating system. The context of an operation may correspond to performing an operation that is a native operating system operation or may be a legacy operating system operation. The processing then continues by setting within a corresponding segment descriptor a paging enable bit for a given segment that corresponds to the operation when the context of the operation corresponds to a legacy operating system. The setting of the paging enable bit is done in accordance with the processing of the native operating system. The processing then continues by processing the segment descriptor via segmentation processing in accordance with the legacy operating system to obtain a linear address. With the paging enable bitd, the linear address is processed to obtain a physical address.

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Oakland, CA, United States of America

Paul W Campbell