Microsoft Technology Licensing, LLC

Paul W Accisano

Kenneth S Reneris

Mark Gary Kupferschmidt

Janet Lynn Schneider

Srinivas Raghu Gatta

Michael Burt Goulding

Daniel Vasquez Lopez

Matus Lipka

Jamie Randall Kuesel

Jason Michael Lee

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Determining critical timing paths in a superconducting circuit design

A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Autoplacement of superconducting devices

Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

Scheduling of tasks for execution in parallel based on geometric reach

A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.

Superconductive circuit splitter placement

Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.

Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

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Paul W Accisano