Real Intent, Inc.

Paul Vyedin

Prakash Narain

Vishnu Vimjam

Vikas Sachdeva

Methods and systems are described to identify potential failures caused by metastability arising from signal propagation between asynchronous clock domains in integrated circuits with multiple operating modes, each mode allowing selected clocks to propagate. Typical integrated circuits have numerous operating modes, and hence numerous possible clock combinations, each combination causing different asynchronous clock-domain crossings, and hence different potential failures. Since verification for even one clock combination is time-consuming, explicitly enumerating and verifying all possible clock combinations is unviable. In practice very few clock combinations are verified, possibly missing failures. The present invention achieves superior performance, scalability, comprehensiveness and precision in verification despite numerous operating modes, due the following insights: (a) The number of possible clock combinations for a transmit-receive signal pair is small relative to the total number of operating modes, and (b) Cause of failure for a transmit-receive pair remain identical across many clock combinations associated with it.

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San Jose, CA, United States of America

Paul Vyedin