Fairchild Semiconductor Corporation

Alpha & Omega Semiconductor Corporation

Alpha and Omega Semiconductor (cayman) Ltd.

Alpha and Omage Semiconductor Inc.

Paul Thorup

Madhur Bobde

Hong Chang

Yeeheng Lee

Wenjun Li

Hongyong Xue

Yiming Gu

Yang Xiang

Hamza Yilmaz

Christopher Boguslaw Kocon

Lingpeng Guan

Dean E Probst

Nathan Lawrence Kraft

Terence Huang

Sekar Ramamoorthy

Xiaobin Wang

Ashok Challa

Bruce Douglas Marchant

Jowei Dun

Christopher Lawrence Rexer

Michael D Gruenhagen

Dixie Dunn

Steven Paul Sapp

Daniel S Calafut

Becky Losee

Robert Herrick

A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.

Trench MOSFET device and the preparation method thereof

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Power device with high aspect ratio trench contacts and submicron pitches between trenches

A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.

A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Split-gate trench power mosfet with protected shield oxide

Split-gate trench power MOSFET with protected shield oxide

A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.

High density FET with integrated Schottky

In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Field effect transistor and schottky diode structures

A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.

Shield contacts in a shielded gate MOSFET

A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.

Shielded gate trench FET with the shield and gate electrodes connected together in non-active region

A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween.

Method of forming high density trench FET with integrated Schottky diode

A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.

Method for forming a shielded gate trench FET with the shield and gate electrodes being connected together

A monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A source region of the first conductivity type is located over each body region. A contact opening extends between the pair of trenches to a depth below the source regions. An interconnect layer fills the contact opening so as to electrically contact the source regions and the second silicon region. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.

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West Jordan, UT, United States of America

Paul Thorup