Hewlett Packard Enterprise Development LP

Silicon Graphics, Incorporated

Cray Incorporated

Paul T Wildes

Hyunjun Kim

Andy Becker

Andrew J Becker

Shawn Utz

Mark S Birrittella

Gregory E Scott

Jim Fitzke

Edward J O'Neill

Brad Smith

One embodiment provides a printed circuit board (PCB). The PCB can include one or more metal layers and at least a pair of differential transmission lines. The pair of differential transmission lines can include a first transmission line and a second transmission line. The first transmission line can include a plurality of timing-skew-compensation structures, and a respective timing-skew-compensation structure of the first transmission line or a corresponding segment of the second transmission line adjacent to the timing-skew-compensation structure has a non-uniform width.

Skew compensation apparatus for controlling transmission line impedance

One embodiment can provide a method and system for compensating for timing skew in a differential pair transmission line on a printed circuit board (PCB). During operation, the system obtains a PCB comprising one or more layers and at least a differential pair transmission line. The differential pair transmission line comprises first and second transmission lines, with a respective transmission line coupled to at least one via extending through the one or more layers of the PCB. The system determines a difference in length between first and second transmission lines and determines a stub length of the at least one via based on the determined difference in length between the first and second transmission lines, thereby compensating for the time skew in the differential pair transmission line.

Asymmetric differential via stubs for skew compensation

Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.

Method for cross-talk reduction technique with fine pitch vias

To eliminate signal loss and sources of signal attenuation, a connection methodology is utilized which enables high-speed signals to be directly communicated from particular integrated circuits housed on a printed circuit board, to other locations within a system. More specifically, a signal escape strategy directly connects a high-speed cable to a point on the circuit board which is very close to the integrated circuit itself. A back-side connection methodology is utilized so that electrical signals pass directly from the integrated circuit through a via, to a connection point on the backside of the circuit board. To accommodate this connection, a specially designed interposer and related paddle cards are utilized so the high-speed communication cable can be easily attached.

Direct connection of high speed signals on PCB chip

A printed circuit board includes additional stitching vias placed at strategic location within a connection matrix, which provides additional isolation and further accommodates high-speed communication capabilities. The stitching vias have a variable length or depth, depending on related structures within the circuit board, so as to avoid any interference with underlining escape routing, or alternative signal transmission structures. More specifically, these stitching vias help to eliminate cross-talk in the via field caused by the close proximity of signal carrying structures. Further, differential signal communication is better accommodated based upon this reduction in cross-talk.

PCB with minimized crosstalk

The various structures forming communication paths on a printed circuit board can create several undesired effects, especially when high frequency signals are considered. Non-functional pads created during the manufacturing process have the potential to create an undesired effect, but when the overall collection of non-functional pads are carefully configured, an optimized communication path can be formed. More specifically, by selectively removing some collection of the non-functional pads, the high frequency characteristics of the communication paths can be optimized.

Method for impedance compensation in printed circuit boards

The present invention provides a system for efficient, high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock. The digital system also has a synchronizing clock that operates at the same frequency as the forwarded clock. When the data arrives at the receive module it is captured by a pair of memory devices operating on different phases of the capture clock. The memory devices feed the data to a multiplexor that selects, as a function of the synchronizing clock, between the outputs of the two memory devices. At this point the data has been synchronized with the system clock and can be captured using the system clock for processing in the receive module.

Circuit design for high-speed digital communication

A method for determining optimum locations for scan latches using traditional fault-simulation and some additional 'bookkeeping.' A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A high count of faults indicates high observability at that point. This can be further refined by looking at total faults covered by given sets of latches. This permits maximizing fault coverage while minimizing resources. In addition, the software can keep a transition count at each latch's output, to enable the already established method of using transition counts to measure testability. A low transition count indicates a desirable place for a scan latch.

Growing community of inventors

Eau Claire, WI, United States of America

Paul T Wildes