Xilinx, Inc.

Dynalogic

Dynachip Corporation

Paul T Sasaki

Suresh M Menon

Atul V Ghia

Jason R Bergendahl

Hare Krishna Verma

Warren E Cory

Jian Tan

Tsung C Whang

Steven P Young

Trevor J Bauer

Ping-Chen Liu

Philip M Freidin

Ketan Sodha

Madhukar B Vora

Vasisht Mantra Vadi

Burnell G West

Adebabay M Bekele

Paul Y Wu

Romi Mayder

Philip D Costello

Arch Zaliznyak

Qi Zhang

Christopher Paul Wyland

Hassan K Bazargan

Madan Mohan Patra

Santiago G Asuncion

Maden M Patra

A memory write interface in an integrated circuit (IC) and method of providing the same are described. An aspect relates to an apparatus for providing an input/output (IO) interface in a programmable device. The apparatus can include: a memory write interface configured to drive a memory having a daisy-chained clock, a first interface configured to receive output data from the programmable device and a second interface configured to control transmission of the output data to the memory by an IO element of the programmable device, the first interface operating according to a global clock of the programmable device and the second interface operating according to a local clock used only by the IO interface; a delay circuit configured to add a delay to the local clock with respect to the global clock; and a configuration circuit configured to adjust the delay added to the local clock to implement write-leveling at the memory.

Memory write interface in an integrated circuit and method of providing same

In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Power distribution network

A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.

Method and apparatus for detecting and correcting errors in a parallel to serial circuit

Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

Regional signal-distribution network for an integrated circuit

Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input cell with a second delay chain and a second register block is provided for receipt of a data signal by the second delay chain. The second input cell is configured such that output from the second delay chain is coupled to a data input of the second register block. The first input cell and the second input cell may be operated in either a first modality or a second modality. The first modality may be for interfacing to a synchronous integrated circuit interface. The second modality may be for interfacing to a synchronous network/telecommunications interface.

Bimodal source synchronous interface

Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

High speed configurable transceiver architecture

Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Network physical layer with embedded multi-standard CRC generator

A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Multi-purpose source synchronous interface circuitry

Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate ('SDR') data, and the latter configuration is for Double Data Rate ('DDR') data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

Bimodal serial to parallel converter with bitslip controller

A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.

Variable data width operation in multi-gigabit transceivers on a programmable logic device

Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable active driver circuits are employed. These circuits eliminate essentially all of the resistance present in prior art passive connections.

High speed programmable logic architecture

A logic cell for a programmable logic device that features a random access memory adapted to selectively function as additional logic functions for the logic cell or one of a several different types of random access memory. For example, the random access memory may be configured to provide AND-OR logic functions or as a 32&times;1 single input port random access memory, two 16&times;1 single input port random access memories or a 32&times;1 dual input port memory.

Programmable logic device

An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster 'time to market'.

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Sunnyvale, CA, United States of America

Paul T Sasaki