Skyworks Solutions, Inc.

Paul T DiCarlo

Dylan Charles Bartle

Florinel G Balteanu

David Scott Whitefield

Hailing Wang

Yu Zhu

Hanching Fuh

Jerod F Mason

Oleksiy Klimashov

Boshi Jin

Serge Francois Drogi

Steven Christopher Sprinkle

Ping Li

David Richard Pehlke

Michael David Hill

Grant Darcy Poulin

Craig Joseph Christmas

Luigi Panseri

Kim Rene Smith

Atiqul Baree

David Steven Ripley

William John Domino

Yun Shi

David T Petzold

Christian Cojocaru

Dogan Gunes

Jing-Hwa Chen

Gong Bin Tang

Dima Prikhodko

Gene A Tkachenko

Steven P Boerman

Patrice Reginella

Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Switch with gate or body connected linearizer

The present disclosure relates to a radio frequency circuit comprising a linearizer circuit. The linearizer circuit may comprise a first capacitor and a second capacitor arranged in parallel. The first capacitor may have a positive third order derivative of charge with respect to voltage. The second capacitor may have a negative third order derivative of charge with respect to voltage. Related radio frequency modules and wireless communication devices are also disclosed.

Radio frequency circuit having a linearizer

Apparatus and methods for diplexing by antenna structure are provided. In certain embodiments, a mobile device includes a front end system and an antenna structure. The front end system includes a first signal conditioning circuit configured to condition a first radio frequency signal of a first frequency, and a second signal conditioning circuit configured to condition a second radio frequency signal of a second frequency that is lower than the first frequency. The antenna structure is configured to diplex the first radio frequency signal and the second radio frequency signal, and includes a first antenna configured to handle the first radio frequency signal and a second antenna electromagnetically coupled to the first antenna and configured to handle the second radio frequency signal.

Apparatus and methods for diplexing by antenna structure

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Main-auxiliary field-effect transistor configurations

Reconfigurable patch antenna systems are provided herein. In certain embodiments, a mobile device includes a patch antenna configured to handle a radio frequency signal at a signal feed. The patch antenna includes a plurality of antenna segments. The front-end system further includes a plurality of switches each configured to control connection of a respective one of the first plurality of antenna segments to the first signal feed, and a control circuit configured to control the plurality of switches to provide a frequency adjustment to the patch antenna.

Patch antenna with reconfigurable size for frequency control

Apparatus and methods for wirelessly communicating using antennas are disclosed. In certain embodiments, an antenna system includes a first radio frequency signal conditioning circuit configured to condition a first radio frequency signal of a first frequency, a plurality of second radio frequency signal conditioning circuits configured to condition a plurality of second radio frequency signals of a second frequency that is greater than the first frequency, a plurality of switches operable in a first mode and a second mode, and an antenna array of including a plurality of antenna elements interconnect by the plurality of switches. The antenna array is operable to handle the first radio frequency signal in the first mode, and to handle the plurality of second radio frequency signals in the second mode.

Frequency range two antenna array with switches for joining antennas for frequency range one communications

Apparatus and methods for envelope controlled radio frequency (RF) switches are provided. In certain embodiments, a power amplifier provides an RF signal to an antenna by way of an RF switch. Additionally, the envelope signal is used not only to control a power amplifier supply voltage of the power amplifier, but also to control a regulated voltage used to turn on the RF switch. For example, a level shifter can use a regulated voltage from charge pump circuitry to turn on the RF switch, and the envelope signal can be provided to the charge pump circuitry and used to control the voltage level of the regulated voltage over time.

Envelope controlled radio frequency switches

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both Hand Hsimultaneously.

Switch linearization with asymmetrical anti-series varactor pair

Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).

Switches with voltage level shifters in radio frequency applications

Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal that is substantially triangular along an envelope path, and by providing an RF signal to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.

Envelope alignment calibration in radio frequency systems

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Fabricating field-effect transistors with interleaved source and drain finger configuration

A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.

Cascode amplifier optimization

Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Apparatus and methods for multi-antenna communications

Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

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Marlborough, MA, United States of America

Paul T DiCarlo