Finisar Corporation

Paul Sung

Dmitri Bannikov

Alex Fishman

Serguei Dorofeev

Konstantinos G Haritos

A distributed computing environment for calibrating multiple components and reliably generating calibration data about each of the components. The calibration data from a plurality of calibration devices is stored in a database in a manner that avoids the problem of data collisions. The calibration devices include specific components or modules that allow each calibration device to independently generate calibration data, buffer calibration data, archive calibration data, transmit and receive data signals from a database, and receive data signals from a global network and display them for an operator. A method is disclosed which generated calibration data and subsequently detects and corrects calibration errors within a distributed network in a time frame that avoids the unnecessary disposal of improperly calibrated devices.

Automatic detection of production and manufacturing data corruption

The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability to test the operation of an electronic device's transmitter and receiver circuitry. Data generated by a BERT is transmitted in an electrical form to a DUT and a master device. The DUT transmits data received in an electrical form to the master device in an optical form and the master device transmits data received in an electrical form to the DUT in an optical form. The master device and the DUT then transmit data received in an optical form back to the BERT in an electrical form. The data received from the DUT and the master device, respectively, is separately tested for bit errors. Do so enables to calculation of bit error rates for two distinguishable data paths through the DUT.

System and method of detecting a bit processing error

Systems and methods for testing bit processing capacities of electronic devices and for reducing or eliminating jitter that compromises the ability of electronic devices to perform this task. Embodiments include circuitry and a methodology for locating and employing a data signal delay&#x2014;in conjunction with a latch&#x2014;to reduce or eliminate jitter from serial encoded data generated by a serializer/deserializer. The data signal delay ensures that the latch latches a state of the serial encoded data at a position within a data signal cycle of minimum jitter.

Growing community of inventors

Saratoga, CA, United States of America

Paul Sung