Varian Semiconductor Equipment Associates, Inc.

Paul Sullivan

Paul J Murphy

Connie P Wang

Steven Raymond Walther

Peter Nunan

Nicholas P T Bateman

William Tyler Weaver

Atul Gupta

Kasegn D Tekletsadik

Sukti Chatterjee

Yuri Erokhin

Bharatwaj Ramakrishnan

Ludovic Godet

Frank Sinclair

Joseph C Olson

Morgan Evans

Charles T Carlson

John W Graff

James Paul Buonodono

Nicholas Pt Bateman

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

Integrated superconductor device and method of fabrication

In one embodiment, a method to form a superconductor device includes depositing a crystalline layer having a preferred crystallographic orientation on a substrate and forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer. A metallic layer is formed on the superconductor layer and a mask is provided proximate the substrate to define a protected portion of the oriented superconductor layer and an exposed portion of the oriented superconductor layer. The exposed portion of the oriented superconductor layer is removed without etching the protected portion of the oriented superconductor layer.

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.

High temperature superconductor tape with alloy metal coating

A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.

Laser processing of superconductor layers

A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.

Ion implantation for superconductor tape fabrication

A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.

Low AC loss high temperature superconductor tape

One embodiment of this ion implanter includes an ion source and a process chamber. This process chamber is connected to the ion source and separated from the ion source by a plurality of extraction electrodes. A carrier holds multiple workpieces. A mask loader in the process chamber connects a mask to the carrier. A transfer chamber and load lock may be connected to the process chamber. The ion implanter is configured to perform either blanket or selective implantation of the workpieces.

High-throughput ion implanter

The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate.

Substrate processing based on resistivity measurements

Methods to form complementary implant regions in a workpiece are disclosed. A mask may be aligned with respect to implanted or doped regions on the workpiece. The mask also may be aligned with respect to surface modifications on the workpiece, such as deposits or etched regions. A masking material also may be deposited on the implanted regions using the mask. The workpiece may be a solar cell.

Implant alignment through a mask

Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembly segment between the particle source and the solar cell; and selectively implanting first type dopants traveling through the aperture into a first region of the solar cell while minimizing introduction of the first type dopants into a region outside of the first region.

Patterned assembly for manufacturing a solar cell and a method thereof

A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.

Wafer bonding activated by ion implantation

The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the solar cell. In another embodiment, two different species are successively implanted without breaking vacuum. In another embodiment, the substrate is implanted, then flipped such that it can be and implanted on both sides before being annealed. In yet another embodiment, one or more different masks are applied and successive implantations are performed without breaking the vacuum condition, thereby reducing the process time.

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Wenham, MA, United States of America

Paul Sullivan