Koninklijke Philips Corporation N.v.

Vector Fabrics B.v.

Nxp B.v.

Synopsys, Inc.

Paul Stravers

Peter Deixler

Cornelis Jojakim Jalink

Jan Hoogerbrugge

Geert Willem Van Der Veen

Martijn Rutten

Jos Van Eijndhoven

Maurice Kastelijn

Jan-Willem Van De Waerdt

Adrianus Josephus Bink

Tommy Kamps

Alexey Rodriguez

Jayram Moorkanikara Nageswaran

Wouter Swierstra

A memory protection unit (MPU) configuration request may be received, where the MPU configuration request may include a memory protection rule. A first entry in a first MPU circuit may be determined which matches the memory protection rule. A compliance result may be determined based on checking if the memory protection rule complies with the first entry. The memory protection rule may be written in a second MPU circuit based on the compliance result.

Memory protection unit with secure delegation

Disclosed is a light source having a plurality of light elements and a control system for controlling the light elements. The control system includes a plurality of light element controllers, each connected to a respective light element, and arranged to obtain light element data; and a bus interface, which is connected to the light element controllers via a light source bus. The bus interface provides the light element controllers with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

Light source luminaire system light element control

A method of generating an embedded system () from an original computer program () which embedded system () provides a parallellized hardware () and software () implementation of the original computer program (), which parallellized implementation () satisfies one or more criteria regarding hardware constraints of the embedded system (). The system provides partitioning of functionality from the original computer program () using structural and behavioral program models and detects streaming and memory dependencies to improve the partitioning, relying on added indications of source lines and variables in said original computer program to relate partitions and dependencies in the program model with locations in the original program source code.

Embedded system performance

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.

Embedded system development

Light source having a plurality of light elements () and a control system for controlling the light elements. The control system comprises a plurality of light element controllers (), each connected to a respective light element (), and arranged to obtain light element data; and a bus interface (), which is connected to the light element controllers () via a light source bus (). The bus interface () provides the light element controllers () with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

Light source luminaire system light element control by symbol tag interpreter

A light source having a plurality of light elements and a control system for controlling the light elements. The control system comprises a plurality of light element controllers, each connected to a respective light element, and arranged to obtain light element data; and a bus interface, which is connected to the light element controllers via a light source bus. The bus interface provides the light element controllers with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

Controllable light source having a plurality of light elements

An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

Intergrated circuit and a method of cache remapping

A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interrupt controller interface. Interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller. From the plurality of interrupt requests and the second selected interrupt request, a first single interrupt request is selected and transmitted to the processing unit along with a first priority signal, and a first index signal. The processing unit initiates an appropriate interrupt service routine on the basis of said first index signal.

Data processing system with interrupt controller and interrupt controlling method

The invention is based on the idea that for a large data structure with N entries, memory space for the locks corresponding to the entries can be saved by performing a hashing function on a value that represents an entry into a hashed value 1 to M. This hashed value is used to index the table of M locks. The value of M is typically much smaller than the value of N thereby reducing memory space requirements. If M is chosen large enough and a good hashing function is selected, problems with collisions will be very small. Additionally, problems relating to deadlock occurring, when the hashed value of a second entry equals the hashed value of a first entry, are being addressed by swapping the hashed values of the first and second entries, when the hashed value of the second entry is smaller than the hashed value of the first entry.

Entry locking for large data structures

An instruction execution device and method are disclosed for reducing register write traffic within a processor. The instruction execution device includes an instruction pipeline for producing a result for an instruction, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, and a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction.

System and method for eliminating write back to register using dead field indicator

An instruction execution device and method are disclosed for reducing register write traffic within a processor with exception routines. The instruction execution device includes an instruction pipeline for producing a result for an instruction, wherein the exception routines may interrupt the instruction pipeline a random intervals, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction, a First in First out (FIFO) buffer for storing the result and a FIFO control for writing the contents of the FIFO buffer to the register file when an exception occurs.

System and method for eliminating write backs with buffer for exception processing

A data processing apparatus has a main memory that contains memory locations with mutually different access latencies. Information from the main memory is cached in a cache memory. When cache replacement is needed selection of a cache replacement location depends on differences in the access latencies of the main memory locations for which replaceable cache locations are in use. When an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations cached in other replaceable cache memory locations, the cached data for that main memory location is replaced by preference over data for the other main memory locations, because of its smaller latency.

Data processing apparatus with a cache memory and method of using such an apparatus

A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions are directly available for use, without a memory address computation, and a prediction scheme based on this directly available information is particularly well suited for a pipeline architecture. Indirect addressing instructions also provide a higher-level abstraction of memory accesses, and are likely to be more indicative of relationships among data items, as compared to the absolute address of the data items. In a preferred embodiment, the base register that is contained in the indirect address instruction provides an index to a way-prediction table for an n-way associative cache. Data items that are indirectly addressed using the same base register are likely to be related, and thus predicting a particular way in an n-way associative memory based on the base register of an indirect address instruction is likely to result in a cache-hit, thereby reducing the energy consumption associated with accessing all ways in the cache.

Growing community of inventors

Eindhoven, Netherlands

Paul Stravers