International Business Machines Corporation

Paul Steven Zuchowski

Scott Whitney Gould

John Maxwell Cohn

Stephen Gerard Shuma

Kenneth Joseph Goodnow

Douglas Willard Stout

David E Lackey

Thomas R Bednar

Peter Albert Twombly

Mark Steven Styduhar

Oscar Conrad Strohacker

Corey Kenneth Barrows

Jeannie H Panner

Peter Anton Habitz

Ivan L Wemple

Anne Elizabeth Gattiker

Phil Nigh

Franco Motika

Robert J Allen

Douglas Wayne Kemerer

Marc Douglas Knox

Jody John Van Horn

William John Livingstone

David A Grosch

Sebastian Theodore Ventrone

Gustavo Enrique Tellez

Christopher B Reynolds

Paul E Dunn

Andrew S Wienick

Chandramouili Visweswariah

Michael Richard Ouellette

Juergen Koehl

William C Leipold

Laura R Darden

William F Smith

Steven H Voldman

Chandramouli Visweswariah

Clarence Rosser Ogilvie

Steven Frederick Oakland

Ronald Dennis Rose

Leon Jacob Sigal

Larry Wissel

Leah M P Pastel

Patrick Edward Perry

Brian A Worth

Erich C Schanzenbach

James Venuto

Amol Anil Joshi

Andrew D Huber

William F Pokorny

Frank O Distler

John E Barwin, Iii

Jose L P Neves

Jose Luis Pontes Correia Neves

Bruce Cowan

Jody John VanHorn

Mark F Ollive

Daniel Joseph Mainiero

Kevin Grosselfinger

James J Engel

Bruce D Raymond

Jason Chung

Debra K Korejwa

Philip S Homsinger

Dora R Pealer

Thomas R Bedner

Michael Timothy Trick

A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested 'at speed' during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

Method and device for selectively adding timing margin in an integrated circuit

A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

On-demand power supply current modification system and method for an integrated circuit

A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

Structure for an on-demand power supply current modification system for an integrated circuit

Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Structure for system for extending the useful life of another system

In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Method and apparatus for manufacturing diamond shaped chips

A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit

The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

Mechanism for detection and compensation of NBTI induced threshold degradation

Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Method and system for extending the useful life of another system

A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

Method for increasing the manufacturing yield of programmable logic devices

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Integrated circuit testing methods using well bias modification

A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

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Jericho, VT, United States of America

Paul Steven Zuchowski