International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Paul Stephen McLaughlin

Hazara Singh Rathore

Baozhen Li

Jason Paul Gill

Timothy Dooling Sullivan

Ping-Chuan Wang

Ronald G Filippi

Kaushik Chanda

Du Binh Nguyen

Chih-Chao Yang

Lawrence Alfred Clevenger

Thomas M Shaw

Conal Eugene Murray

Vincent James McGahay

Chao-Kun Hu

Andrew P Cowley

Theodorus E Standaert

Tom C Lee

Stephen Edward Greco

Birendra N Agarwala

Sujatha Sankaran

Ronald Gene Filippi, Jr

Anthony K Stamper

Yun Yu Wang

Christopher David Muzzy

Elbert Emin Huang

Griselda Bonilla

Hormazdyar M Dalal

Paul David Agnello

Terence Lawrence Kane

John Patrick Hummel

Leena Paivikki Buchwalter

Richard Andre Wachnik

Jean E Wynne

Richard G Smith

Barbara Jean Luther

Alexander J Swinton

Dirk Karl Manger

Christian Lavoie

Timothy Harrison Daubenspeck

Andrew Herbert Simon

Gregory John Uhlmann

Ahmet Serkan Ozcan

Peter Anton Habitz

Jeanne P Bickford

Norman Jay Rohrer

James Douglas Warnock

Roger Allan Quon

Erik L Hedberg

Gregory Gower Freeman

Stephan Grunow

Jin-Ping Han

Shawn Peter Fetterolf

Siyuranga O Koswatta

J Campbell Scott

Robert Daniel Edwards

Tibor Bolom

Dae Young Jung

Daniel J Poindexter

Conrad A Barile

Dae-Young Jung

James D Werking

Judith A Wright

Dileep N Netrabile

Scott Taylor

Dae-Young c/o Ibm United Kingdom Lim Jung

Erik Leigh Hedberg

Jean Elizabeth c/o Ibm United Kingdom Lim Wynne

Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Metallic synapses for neuromorphic and evolvable hardware

A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.

Electromigration test structure for Cu barrier integrity and blech effect evaluations

A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

Method and structure for determining thermal cycle reliability

A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Electromigration resistant via-to-line interconnect

A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.

Method and system to predict a number of electromigration critical elements

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

Method for prediction of premature dielectric breakdown in a semiconductor

A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.

Method of forming an embedded barrier layer for protection from chemical mechanical polishing process

The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (), at least one conductive fusible link (), first and second connection elements (), and first and second metal lines (). The conductive supporting elements (), the conductive fusible link (), and the metal lines () are located at a first metal level (), while the connect elements () are located at a second, different metal level () and are connected to the conductive supporting elements () and the metal lines () by conductive via stacks () that extend between the first and second metal levels ().

Laser fuse structures for high power applications

A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Structure for modeling stress-induced degradation of conductive interconnects

A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (&#x3bc;m).

Structure for monitoring stress-induced degradation of conductive interconnects

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Poughkeepsie, NY, United States of America

Paul Stephen McLaughlin