International Business Machines Corporation

Johnson and Johnson Vision Care, Inc.

Globalfoundries Inc.

Ultratech, Inc.

Hitachi Chemical Dupont Microsystems, Ltd.

Hitachi Chemicial Dupont Microsystems, L.l.c.

Paul Stephen Andry

John Ulrich Knickerbocker

Cornelia K Tsang

Bucknell Chapman Webb

Bing Dang

Edmund Juris Sprogis

Robert L Wisnieff

Li-Wen Hung

Evan G Colgan

Jeffrey Donald Gelorme

Eric Peter Lewandowski

Chirag Suryakant Patel

Russell Alan Budd

Jae-Woong Nah

Frank Robert Libsch

Yu Luo

Cornelia Kang-I Tsang

Minhua Lu

John Michael Cotte

Steven Lorenz Wright

Praveen Chaudhari

Raymond R Horton

James Patrick Doyle

Shui-Chih Alan Lien

James Andrew Lacey

Yang Liu

Leena Paivikki Buchwalter

Leland Chang

Adam Toner

Katsuyuki Sakuma

Qianwen Chen

Cyril Cabral, Jr

Kenneth Parker Rodbell

Robert David Allen

Lawrence Shungwei Mok

Edward Crandal Cooney, Iii

Qiang Huang

David Earle Seeger

Devendra K Sadana

Anthony K Stamper

Brent A Anderson

Michael S Gordon

Mukta G Farooq

Mark Delorman Schultz

Subramanian Srikanteswara Iyer

Daniel B Otts

Paul Alfred Lauro

James Daniel Riall

Richard Paul Volant

Kamal Kumar Sikka

Benjamin V Fasano

Jon Alfred Casey

Emily R Kinser

Stephen L Buchwalter

Takatoshi Tsujimura

Paul Francis Fortier

Huan Hu

Robert Hannon

Brian Richard Sundlof

Sarah Huffsmith Knickerbocker

Gregory M Fritz

David Hirsch Danovitch

Monty Montague Denneau

John C Collins

Luc Gilbert Guerin

Sherif Ahmed Goma

Jeffrey P Gambino

Daniel C Edelstein

Kevin K Chan

Sampath Purushothaman

Ping-Chuan Wang

Michael A Gaynes

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

Christopher Vincent Jahnes

Eugene John O'Sullivan

Robert K Montoye

Gareth Geoffrey Hougham

Teodor Krassimirov Todorov

Marc Adam Bergendahl

Harm Peter Hofstee

Bruno Michel

Xiao Hu Liu

Thomas J Brunschwiler

Joshua M Rubin

George Frederick Walker

Vijayeshwar Das Khanna

Thomas Anthony Wassick

Alessandro Cesare Callegari

Michael F Lofaro

Hiroyuki Mori

Martin O Sandberg

Kenneth Jay Stein

Douglas C La Tulipe, Jr

Michael Wayne Lane

Kuniaki Sueoka

Peter James Lindgren

John Harold Magerlein

Hanhee Paik

John J Ritsko

A method of forming a thin film battery may include forming may include forming a trench in a substrate, depositing a stencil on top surface of the substrate, wherein the stencil is aligned with the trench, depositing a cathode layer in the trench, wherein the cathode layer is in direct contact with the stencil, and compressing the cathode layer into the trench to reduce a thickness of the cathode layer. The compressing the cathode layer into the trench may include applying isostatic pressure onto the cathode layer using a pressure head. The method may also include depositing an electrolyte layer on top of the cathode layer, depositing an anode layer on top of the electrolyte layer, and depositing an anode collector layer on top of the anode layer.

High capacity compact lithium thin film battery

A composition includes an electrode made of Lithium Manganese Oxyfluoride (LMOF). A single layer separator adheres to a surface of the electrode, is a dielectric that is conductive for Lithium ions but not electrons, and has top and bottom sides. A solid polymer electrolyte (SPE) saturates the electrode so that the LMOF is between 55 percent and 85 percent by mass of a composition of the LMOF electrode and the SPE is between 7.5 percent and 20 percent by mass of the composition of the LMOF electrode. The SPE saturates the separator so that the SPE resides both on the separator top and bottom sides so that the SPE residing on the separator top side contacts the surface. The LMOF exhibits X-Ray Diffraction spectrum peaks between twenty-two and twenty-four 2-theta degrees, between forty-eight and fifty 2-theta degrees, between fifty-four and fifty-six 2-theta degrees, and between fifty-six and fifty-eight 2-theta degrees.

3D textured composite silicon anode and fluorinated lithium compound electrochemical cell

An exemplary method includes at a bonding temperature, bonding a semiconductor chip to an organic laminate substrate using solder; without cooldown from the bonding temperature to room temperature, at an underfill dispense temperature, dispensing underfill between the semiconductor chip and the organic laminate substrate; and curing the underfill within a range of temperatures above the underfill dispense temperature. Another exemplary method includes depositing a first solder on pads of an organic laminate substrate; contacting a second solder on pillars of a semiconductor chip to the first solder on the pads of the organic laminate substrate; and solder bonding the semiconductor chip to the organic laminate substrate.

Assembly of a chip to a substrate

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Direct bonded heterogeneous integration silicon bridge

A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

Transferrable pillar structure for fanout package or interconnect bridge

An energy storage device sits within a trench with electrically insulated sides within a substrate. Within the trench there is an anode, an electrolyte disposed on the anode, and a cathode structure disposed on the electrolyte. Variations of an electrically conductive contact are disposed on and in electrical contact with the cathode structure. At least part of the conductive contact is disposed within the trench and the conductive contact partially seals the anode, electrolyte, and cathode structure within the trench. Conductive and/or non-conductive adhesives are used to complete the seal thereby enabling full working electrochemical devices where singulation of the devices from the substrate enables high control of device dimensionality and footprint.

Encapsulating in-situ energy storage device with electrode contact

Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Handler bonding and debonding for semiconductor dies

A micro-battery is provided in which a metallic sealing layer is used to provide a hermetic seal between an anode side of the micro-battery and the cathode side of the micro-battery. In accordance with the present application, the metallic sealing layer is formed around a perimeter of each metallic anode structure located on the anode side and then the metallic sealing layer is bonded to a solderable metal layer of a wall structure present on the cathode side. The wall structure contains a cavity that exposes a metallic current collector structure, the cavity is filled with battery materials.

Simplified hermetic packaging of a micro-battery

Batteries include an anode structure, a cathode structure, and a conductive overcoat. The anode structure includes an anode substrate, an anode formed on the anode substrate, and an anode conductive liner that is in contact with the anode. The cathode structure includes a cathode substrate, a cathode formed on the cathode substrate, and a cathode conductive liner that is in contact with the cathode. The conductive overcoat is formed over the anode structure and the cathode structure to seal a cavity formed by the anode structure and the cathode structure. At least one of the anode substrate and the cathode substrate is pierced by through vias that are in contact with the respective anode conductive liner or cathode conductive liner.

Microbattery with through-silicon via electrodes

A modular superconducting quantum processor includes a first superconducting chip including a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency, and a second superconducting chip including a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and to the second superconducting chip. The interposer chip has interposer coupler elements configured to couple the second plurality of qubits to the fourth plurality of qubits.

Modular, frequency-flexible, superconducting quantum processor architecture

In one example, a battery includes a negative terminal, a positive terminal, an electrolyte contained between the negative terminal and the positive terminal, and a hydrogel layer positioned between and physically separating the negative terminal and the positive terminal.

Microbattery separator

A method for forming a battery structure includes texturing an anode packaging material to form a first textured surface, depositing one or more metal layers including an anode metal on the first textured surface and forming a separator on the anode metal. It also includes texturing a cathode packaging material to form a second textured surface, depositing a cathode metal on the second textured surface, and forming an electrolyte binder paste on the cathode metal, which contacts the separator with any gap being filled with electrolyte.

Low-profile battery construct with engineered interfaces

An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.

Mixed under bump metallurgy (UBM) interconnect bridge structure

An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Large channel interconnects with through silicon Vias (TSVs) and method for constructing the same

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Paul Stephen Andry