International Business Machines Corporation

Paul Stafford Zerr

Harold Pilo

Steven Harley Lamphier

Ronald DeSales Rossi

Roger Andrew Verhelst

Kevin George Petrunich

Circuit and method are presented for activating/deactivating a special operational mode at power-on of an integrated circuit device having no industry defined test state and/or dedicated test pin. The operational mode is enabled upon powering on the integrated circuit combined with detection of a predefined pattern of a first logic state and a second logic state clocked in successive cycles within a first standard input signal, such as an output enable signal, for a normal operating mode of the device. Special non-functional processing is then performed, such as reading prestored identification data from the integrated circuit and/or testing the integrated circuit via embedded test circuitry including boundary scan or other diagnostic circuitry. This special operational mode is deactivated upon receipt at the integrated circuit device of a second standard input signal, such as a write signal for a random access memory (RAM) device, of a predefined logic state (e.g., write enable state). Deactivating of the special operating mode is transparent to the normal response of the integrated circuit device to the second standard input signal.

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Gilbert, AZ, United States of America

Paul Stafford Zerr