Qualcomm Technologies International, Ltd.

Qualcomm Incorporated

Paul Simon Hoayun

Zhongze Wang

Guoqing Chen

A programmable memorycomprises programmable data bit cells. A data word comprises a group of the programmable data bit cells. A method of configuring patch code in the memorycomprises identifying a first location (e.g. 0x1234) in the programmable memorywhere a patch is required; modifying a data word at the first location to a predetermined data value (e.g. 0xFFFF); writing patch code for the patch at a patch code location (e.g. 0xABCD); and storing the patch code location. The predetermined data value can be, or can map to, a value of an exception instruction of the processorwhich will cause the processorto read from a patch table. The programmable memorycan be a One Time Programmable (OTP) memory.

Patching of programmable memory

A method and apparatus for balancing voltage stress at a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory array is disclosed. A particular cell of the SONOS flash memory array is selected for programming. A first voltage stress associated with a first SONOS transistor is determined if the particular cell is programmed. The first SONOS transistor is included in a first unselected cell of the SONOS flash memory array. A second voltage stress associated with a second SONOS transistor is determined if the particular cell is programmed. The first voltage stress and the second voltage stress are balanced prior to programming the particular cell.

Reduced silicon-oxide-nitride-oxide-silicon (SONOS) flash memory program disturb

A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a multiplexer arranged between the inputs/outputs and the pads, the multiplexer being operable in a first mode in which it maps a first number of the inputs/outputs to a first number of the pads with a first mean spacing between those pads, and a second mode in which it maps a second number of the inputs/outputs to a first number of the pads with a second mean spacing between those pads, wherein the first number is larger than the second number and the first spacing is smaller than the second spacing.

Port spreading

An integrated circuit has registers which it can place in a low power condition in which their state is lost; a power domain capable of reading the registers, the current operating mode of the domain being dependent on the state of the registers; a memory; and a configuration controller for configuring the registers. The configuration controller has access to a set of mappings. Each mapping indicates for bits represented in the memory the state of other bits storable in the registers. The configuration controller is configured to perform a register configuration operation by reading bits from the memory and populating the registers with a corresponding bit state.

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Willingham, United Kingdom

Paul Simon Hoayun