Intel Corporation

Silicon Graphics, Incorporated

Pmc-sierra, Inc.

Mips Technologies, Inc.

Mips Computer Systems, Inc.

Paul S Ries

John H Crawford

Thomas J Riordan

John R Kinsel

Albert M Thaik

Nicholas W McKeown

Costas Calamvokis

Earl A Killian

Edwin L Hudson

A method of facilitating the scheduling of a first multicast request signal of a series of multicast request signals is disclosed, wherein the first request signal is generated to enable the transmission of a multicast data cell by a source port processor to at least one destination port processor. In a preferred embodiment of the invention, the first request signal is received by a roster storage chip associated with a scheduler subsystem. The first request signal has associated therewith a multicast label of a first value and is adapted to schedule transmission of the first multicast cell to the at least one destination port processor at a first time. A roster of the at least one destination port processor to which the first multicast cell is destined is then generated. A dependence distance associated with the first request signal is determined. The dependence distance comprises the numerical value of the difference between a current multicast cell number (CMCN) and a previous multicast cell number (PMCN). The roster and the dependence distance are transmitted to one of the at least one scheduler chips, such transmission causing the roster and the dependence distance to occupy a second tail entry slot of a second circular buffer associated with the one of the at least one scheduler chips. The second tail entry slot has associated therewith a first multicast table index (MTI) comprising a numerical value. The scheduler chip further has associated therewith a head entry slot having associated therewith a second MTI comprising a numerical value. A first numerical parameter comprising the numerical sum of the dependence distance and the first MTI is determined. If the first numerical parameter is higher in value than the second MTI, the first request signal is arbitrated.

Multicast cell scheduling protocol

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Processor chip for using an external clock to generate an internal clock

Processor chip having on-chip circuitry for generating a programmable

Microprocessor architecture for an address translation unit which provides two levels of memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.

Virtual memory management method and apparatus utilizing separate and

A content addressable memory (CAM) for use with a microprocessor allows comparison of the contents of the memory with input data. The CAM further allows certain bits of input data to be ignored from comparison. This feature allows certain bits, such as a bit indicating whether read or write access is allowed to certain information, to be ignored when the system is, for example, in a supervisory mode. Also disclosed is a method of precharging a hit line, which indicates whether or not a match was found in memory during the comparison, in order to increase the speed of the comparison process.

Content addressable memory for microprocessor system

A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

Processor controlled interface with instruction streaming

Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard

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San Jose, CA, United States of America

Paul S Ries