Honeywell International Inc.

Honeywell G.m.b.h.

Paul S Fechner

Keith W Golke

Bradley J Larsen

Cheisan J Yue

Gordon Alan Shaw

Todd A Randazzo

Michael S Liu

Eric E Vogt

Donald Horkheimer

Gregor D Dougal

David S Willits

Romney R Katti

Stephen Frederic Yates

James L Tucker

Nancy E Iwamoto

Daniel Seymour Reed

James D Seefeldt

James Douglas Seefeldt

David Owen Erstad

Steven J Sanders

Weston Roper

Austin Taranta

Gregory D Dougal

David W Zou

A stabilized integrated optical circuit is presented. The stabilized integrated optical circuit includes at least one integrated optical chip formed from at least one inorganic material, a stabilizing-polarizable-fill gas, and an enclosure enclosing the at least one integrated optical chip and the stabilizing-polarizable-fill gas. At least one surface of the at least one integrated optical chip is modified by a treatment with at least one treatment gas selected to stabilize defects on the at least one surface. The stabilizing-polarizable-fill gas includes NO and at least one polarizable material.

Stabilization gas environments in a proton-exchanged lithium niobate optical chip

This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming a gate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

Compact self-aligned implantation transistor edge resistor for SRAM SEU mitigation

Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

ph sensor with bonding agent disposed in a pattern

Embodiments described herein provide for a pH sensor that is configured for use over a pressure and temperature range. The ISFET die of the pH sensor is bonded to the substrate of the pH sensor with a bonding layer that is disposed between the substrate and the ISFET die. The pressure and temperature change across the pressure and temperature range generates an environmental force in the pH sensor. Further, the substrate or the bonding layer or both change volume over the pressure and temperature range, and the substrate or the bonding layer or both are configured such that the volume change induces a counteracting force that opposes at least a portion of the environmental force. The counteracting force is configured to maintain the change in piezoresistance of the ISFET die from the drain to the source to less than 0.5% over the pressure and temperature range.

pH sensor with substrate or bonding layer configured to maintain piezoresistance of the ISFET die

This disclosure is directed to devices, integrated circuits, and methods for sensing radiation. In one example, a device includes an oscillator, configured to deliver a signal via an output at intervals defined by an oscillation frequency, and a counter, connected to the output of the oscillator and configured to count a number of times the comparator delivers the output signal. The oscillator includes a radiation-sensitive cell that applies a resistance. The resistance of the radiation-sensitive cell is configured to vary in response to incident radiation, wherein the oscillation frequency varies based at least in part on the resistance of the radiation-sensitive cell.

Integrated radiation sensitive circuit

A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

Converter for analog inputs

This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

CMOS logic circuit using passive internal body tie bias

This disclosure is directed to devices, integrated circuits, and methods for sensing radiation. In one example, a device includes a radiation sensitive oscillator, configured to deliver a first output signal at intervals defined by a first oscillation frequency that alters in resistance in response to radiation. The device includes a reference oscillator, configured to deliver a reference output signal at a constant reference oscillation frequency. A controller records a first instance of the count from the radiation sensitive oscillator for a duration of time defined by the count from the reference counter; compares a second instance of the count from the radiation sensitive oscillator with the first instance of the count from the radiation sensitive oscillator; and performs a selected action in response to the second instance of the count from the radiation sensitive oscillator varying from the first instance of the count from the radiation sensitive oscillator.

Integrated comparative radiation sensitive circuit

In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.

Programmable electrical fuse with temperature gradient between anode and cathode

A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements.

Method for digital programmable optimization of mixed-signal circuits

This disclosure is directed to devices, integrated circuits, and methods for sensing cumulative radiation doses. In one example, a device includes a cell configured to be set to an initial resistance and to vary in resistance cumulatively in response to incident radiation. The device also includes an output terminal connected to the cell and configured to vary in voltage in response to the resistance of the cell. The device also includes a comparator configured to deliver an output signal in response to the voltage of the output terminal reaching a threshold voltage. The device also includes a cell charging circuit configured to reset the cell to the initial resistance in response to the output signal from the comparator. The device also includes a counter configured to count a number of times the comparator delivers the output signal.

Integrated circuit cumulative dose radiation sensor

Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Neutron detector cell efficiency

A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Direct contact to area efficient body tie process flow

In one embodiment, a metal-semiconductor field effect transistor (MESFET) comprises a first silicon layer, an insulator layer formed on the first silicon layer, and a second silicon layer formed on the insulator layer. A gate region, a source region, and a drain region are formed in the second silicon layer. A first partial trench is formed in the second silicon layer between at least a portion of the gate region and at least a portion of the source region, wherein the first partial trench stops short of the insulator layer. A second partial trench formed in the second silicon layer between at least a portion of the gate region and at least a portion of the drain region, wherein the second partial trench stops short of the insulator layer. First and second oxide spacers are formed in the first and second partial trenches. The first and second oxide spacers and the source region, gate region, and the drain region are substantially planar.

Growing community of inventors

Plymouth, MN, United States of America

Paul S Fechner