Motorola Corporation

General Dynamics C4 Systems, Inc.

Paul Robert Handly

Erwin Perry Comer

Robert I Foster

Robert Francis Yockey

Andrew Daniel Armstrong

Jason Jonathon Moore

Brian Lee Deitrich

Jamey Mario Creary

Steven Robert Emmert

Jan Madsen

A cryptographic system () and methodology executable within the cryptographic system () enable the use of a programmable logic device PLD () in a single chip cryptographic design flow for secure cryptographic services. Methodology for secure configuration of the PLD () within a cryptographic systementails secure configuration and authentication (), functional verification (), configuration key reload capability (), traffic key load capability () using a split key technique, isolation between command and key fill domains for secure key fill () of key material, redundant system instantiation (), and high speed comparison for secure operation.

Secure configuration of programmable logic device

An single event upset (SEU) tolerant system for detecting and correcting an SEU includes a decision element (200) for receiving a plurality of outputs (120) from a plurality of signal generators (105) and producing an output (130) therefrom. The decision element includes voters which provide two levels of voting for the plurality of redundant outputs (120). First-level voters (300) provide intermediate voted outputs (315) which are received by a second-level voter to determine an output (130). An output disabler (400) determines when an output is provided external to the decision element. A plurality of comparators (210) receive intermediate voted outputs (315) from first-level voters and compare with a plurality of outputs from a plurality of signal generators to determine upset detected signals (125). An upset detected signal controls the selection of feedback for an element having experienced an SEU.

Single event upset tolerant system and method

A sequence-controlled digital circuit (21) is presented. The circuit (21) includes a divider (55) and a plurality of transparent latches (51-54) which together form a latch-based sequencer (42). Typically, a clock signal (43) is divided by the divider (55) into an inverted half-clock signal (45) and a non-inverted half-clock signal (44), each enabling alternate latches (51-54) arranged in a cascade. In the cascade, an output of each latch (51-54) drives an input of the following latch (51-54), one such being an inverting output and the rest non-inverting outputs, to form a twisted-loop counter (50). Each output of each latch (51-54) drives a clock input of a flip-flop (61-68), with a serial input signal (46) driving all data inputs, to form a temporal-to-spacial converter (40). Only the divider (55) operates at the rate of the clock signal (43).

Transparent latch-based sequencer and sequence controlling method

A JTAG module (12) includes a master component (20) and any number of slave components (22). The master component (20) includes a TAP controller (24) and related control circuits. Through a control bus (35), the TAP controller (24) on the master component (20) controls boundary-scan registers (18) on the slave components (22). The boundary-scan registers (18) in the slave components (22) form a boundary-scan chain that originates and terminates at the master component (20). TAP controller circuitry may be omitted from the slave components (22). The boundary-scan registers (18) on the master and slave components (20, 22) are partitioned into external sections (26, 34) and internal sections (28, 36). The external sections couple to conductive traces (46) which are accessible from outside the module (12). The internal sections couple to conductive traces (48) which are substantially inaccessible from outside the module (12).

Hierarchically managed boundary-scan testable module and method

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Paul Robert Handly