Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Arm Limited

Lam Research Corporation

Intermolecular, Inc.

Cypress Semiconductor Corporation

Cerfe Labs, Inc.

Globalfoundies Inc.

Adavnced Micro Devices, Inc.

Paul Raymond Besser

Minh Van Ngo

Matthew S Buynoski

Qi Xiang

Eric N Paton

Paul L King

Jinsong Yin

Sergey D Lopatin

Karsten Wieczorek

Nick Kepler

Christy Mei-Chu Woo

Errol Todd Ryan

Srikanteswara Dakshina-Murthy

Pin-Chin Connie Wang

James N Pan

Connie Pin-Chin Wang

Haihong Wang

Simon S Chan

John A Iacoponi

Larry Lingjer Wang

Simon Siu-Sing Chan

William S Brennan

Darrell M Erb

George Jonathan Kluth

Susan H Chen

Jeremy Isaac Martin

Nicholas John Kepler

Angela Tai Hui

Xunyuan Zhang

Frederick N Hause

Ming-Ren Lin

Lu You

Khanh Q Tran

Minh Quoc Tran

Ming He

Wen Yu

Vivian Ryan

Peter J Beckage

Christy M-c Woo

Hoon Sik Kim

Robin W Cheung

Suzette Keefe Pangrle

Thorsten E Kammler

Minh-Van Ngo

Bhanwar Singh

Kisik Choi

Olov B Karlsson

Ashish Bodke

Fred N Hause

Jinping Liu

Subhash Gupta

Richard J Huang

Scott D Luning

William George En

Shekhar Pramanick

Darin A Chan

Jung-Suk Goo

Robert A Huertas

Sean Xuan Lin

Hieu T Pham

Amol Ramesh Joshi

John Espinoza Sanchez, Jr

David E Brown

Guarionex Morales

Jacques J Bertrand

Jayendra D Bhakta

Ercan Adem

Ming Lin

Carmen L Morales

Jingyan Zhang

Takeshi Nogami

Cyril Cabral, Jr

Christian Lavoie

Zoran Krivokapic

Kenneth Parker Rodbell

Bart Jan Van Schravendijk

Thorsten B Lill

Yowjuang William Liu

Jeffrey Allan Shields

Stephen Mark Rossnagel

Stephan Kronholz

Ning Cheng

Richard C Blish

John S Foster

Jolanta Bozena Celinska

Akif Sultan

Sanjay Gopinath

Shankar Sinha

Gerardo Delgadino

Mark V Raymond

Edward L Haywood

Mehrdad Mahanpour

Raymond T Lee

Igor V Peidous

Diana M Schonauer

Yoshie Kimura

Jeff P Erhardt

Kevin Kashefi

Berthold Reimer

Dengliang Yang

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, an insulative material may be formed on or over a sidewall portion of a conductive contact region. The insulative material may insulate the conductive contact region from resputtered CEM occurring during a physical etch of a CEM film.

Correlated electron material (CEM) devices with contact region sidewall insulation

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.

Formation of correlated electron material (CEM) devices with restored sidewall regions

Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate; forming a layer of a correlated electron material on the conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; and patterning the layers whereby to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the patterning comprises the following steps: forming a hard mask on the layer of the conductive overlay; dry etching the layer of conductive overlay and the layer of correlated electron material whereby to form a partially formed stack; depositing a coating of a protective polymer over at least sidewalls of the partially formed stack; and dry etching the layer of conductive substrate.

Method for fabrication of a CEM device

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments a method may include forming a structure on a first portion of a substrate while maintaining a second portion of the substrate exposed. A sealing layer may be deposited over the structure and over at least a portion of the exposed second portion of the substrate. A conductive via may be formed by way of a dry etch through the sealing layer to contact the exposed metal layer. In embodiments, an etch-stop control layer may be utilized to control an etching process prior to formation of metal contacts over the CEM switch and the conductive via.

Fabrication of correlated electron material (CEM) devices

Disclosed is a method for the fabrication of a correlated electron material (CEM) device comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; patterning these layers to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, on the substrate; forming a cover layer of an insulating material over the stack; and patterning the cover layer wherein: the patterning of the cover layer comprises etching a trench in the cover layer whereby to expose the conductive overlay; and the method further comprises treating the exposed conductive overlay to remove an oxidation layer there from.

ALD of HfAlCfilms using hafnium chloride (HfCl) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfClpulse time allows for control of the Al % incorporation in the HfAlCfilm in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfAlCwork function layer coupled with ALD deposited HfOhigh-k gate dielectric layers was quantified to be mid-gap at &#x2dc;4.6 eV. Thus, HfAlCis a promising metal gate work function material allowing for the tuning of device threshold voltages (V) for anticipated multi-Vintegrated circuit (IC) devices.

Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices

A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and p-type metal oxide semiconductor field effect transistors (PMOSFETs), wherein channel regions of the NMOSFETs and the PMOSFETs include germanium; b) depositing and patterning a mask layer to mask the channel regions of the PMOSFETs and to not mask the channel regions of the NMOSFETs; c) passivating an exposed surface of the substrate; d) removing the mask layer; and e) depositing a metal contact layer on both the NMOSFETs and the PMOSFETs.

Method for integrating germanides in high performance integrated circuits

A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

Air gap spacer integration for improved fin device performance

Methods of lightly implanting platinum, iridium, osmium, erbium, ytterbium, dysprosium, and gadolinium in semiconductor material in shallow depths by plasma-immersion ion implantation (PIII) and/or pulsed PIII are provided herein. Methods include depositing a liner layer prior to masking and implanting features to form n-type and p-type semiconductors and implanting materials through the liner layer. Methods are suitable for integration schemes involving fabrication of fin-type field effect transistors (FinFETs).

Contact integration for reduced interface and series contact resistance

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

Multi-layer barrier layer for interconnect structure

A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450&#xb0; C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.

Method for manufacturing a contact for a semiconductor component and related structure

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Methods for fabricating integrated circuits including fluorine incorporation

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Growing community of inventors

Sunnyvale, CA, United States of America

Paul Raymond Besser