Intel Corporation

Paul R Start

Ravindranath Vithal Mahajan

Digvijay Ashokkumar Raorane

Aditya Sundoctor Vaidya

Rahul N Manepalli

Ram S Viswanath

Rajasekaran Swaminathan

Sriram Srinivasan

Rajen S Sidhu

Sairam Agraharam

Xavier Francois Brun

Nisha Ananthakrishnan

Kaizad Rumy Mistry

Syadwad Jain

Zhizhong Tang

Liwei Wang

Yawei Liang

Jigneshkumar P Patel

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Embedded bridge die with through-silicon vias

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Embedded bridge with through-silicon vias

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Embedded bridge with through-silicon Vias

An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Methods of forming ultra thin package structures including low temperature solder and structures formed therby

Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed.

Molded heat spreaders

An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.

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Chandler, AZ, United States of America

Paul R Start