Mostek Corporation

Bell Telephone Laboratories

Paul R Schroeder

Robert J Proebsting

Sargent S Eaton, Jr

A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row. The least significant bit of the six column address inputs is used to make the final one out of two selection of the sense amplifier and thus the cell from which data is to be read or in which data is to be written. The decoder includes circuit means for storing the decode signal identifying a selected row while subsequent column address signals are input to the chip and decoded by the same decoder. Row address data is first input through the six address pins to the chip; the six inputs are sampled and latched in six address buffers; and the six address inputs are then decoded so that a single row enable line is selected and held active dynamically. Then while data is read from all storage cells in the active row by the sense amplifiers, column address signals applied to the same input pins for the chip are sampled and latched in the same six address buffers, and decoded by the same decoder to select and hold a column enable line active.

MOSFET Random access memory chip

The disclosed read only memory is formed in a two-dimensional matrix comprised of active areas disposed in parallel columns and of conductive layers disposed in rows transverse to the columns. A field-effect transistor is formed at each intersection of a column and a row. The rows of conductive layers are closely packed so that adjacent transistor channels abut one another.

High density read only memory

A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.

Refresh counter

MOSFET Memory chip with single decoder and bi-level interconnect lines

A low power high sensitivity detector having two pairs of cross coupled transistors and voltage equalization circuitry forms the basic configuration of a detector-level shifter circuit and a sense-refresh detector circuit which are both compatible with today's single chip large capacity MOS memories.

Level shifter and sense-refresh detector

An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level. The circuit includes a system for protecting against input voltage undershoot which includes another capacitive input storage node with a first trapping transistor between the logic input to the circuit and the second storage node and a second trapping transistor between the second storage node and the data input storage node. This prevents any degradation of voltage level on the data storage node should the input logic level momentarily be pulled more than one threshold below the level, typically ground, to which the gates of the transistors are taken after the voltage is trapped on the data node.

MOSFET buffer for TTL logic input and method of operation

A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal. The second transistor is held on by a precharge signal so that the first node is held low until the bootstrap node has been charged to the input voltage. Then both the third node and the gate of the second transistor are discharged to turn the second and third transistors off, thus permitting the bootstrap node to go rapidly above the drain supply voltage. The bootstrap node may be used directly as output, or can drive the gate of an output transistor so as to produce a very rapidly rising output which quickly reaches the full drain supply voltage. Circuit means is also provided to discharge the third node to disable the output before an input signal occurs. Since the third node is automatically discharged after receiving an input, the input may subsequently be changed without changing the output. Circuit means is also provided to selectively discharge the bootstrap node to isolate the output after it has achieved maximum voltage, so that the output can be capacitively boosted above the drain supply voltage. A circuit is also provided to reset the output to zero volts in conjunction with isolation of the output. A clock generator employing the various functions of a plurality of cascaded delay stages is also disclosed to demonstrate the capabilities of producing a series of clock pulses which go to V.sub.DD in timed sequence in response to input signal, of producing a voltage substantially above V.sub.DD, and of producing a pulse of predetermined duration.

Clock generator and delay stage

An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a variable resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other digit line. As a result, one of the digit lines has a slightly higher voltage than the other. The first set of transistors permit the latching node to be very rapidly brought to ground in order to completely discharge the digit line having the lower voltage, while maintaining substantially the initial high voltage on the other digit line. The common gate nodes of the first transistors are precharged to the drain supply voltage when one of the true or complement digit lines in each column is low and then isolated to provide bootstrapping above V.sub.DD when the digit lines are subsequently precharged to the drain supply voltage of the system. The split digit lines are precharged from a common node through a first pair of transistors, with the common node being charged through a third transistor. The third transistor is turned off before the first pair of transistors to prevent noise in the drain supply voltage from resulting in uneven voltage precharges on the split data lines.

Dynamic random access memory system

An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a varible resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other line. As a result, one of the digit lines has a slightly higher voltage than the other. The first set of transistors permit the latching node to be very rapidly brought to ground in order to completely discharge the digit line having the lower voltage, while maintaining substantially the initial high voltage on the other digit line. The common gate nodes of the first transistors are precharged to the drain supply voltage when one of the true or complement digit lines in each column is low and then isolated to provide bootstrapping above V.sub.DD when the digit lines are subsequently precharged to the drain supply voltage of the system. The split digit lines are precharged from a common node through a first pair of transistors, with the common node being charged through a third transistor. The third transistor is turned off before the first pair of transistors to prevent noise in the drain supply voltage from resulting in uneven voltage precharges on the split data lines.

A relatively high sensitivity and high speed current detector consists of essentially a common base differential amplifier consistng of two junction transistors, each having separate emitter and collector resistors, and a constant current source connected to the collector resistors. Separate input terminals connected to the emitters allow complementary information current signals or an information current signal and a reference current signal to be applied to the emitter terminals. The output signal and the complement thereof appear at their respective collectors.

High speed current detection amplifier circuit

An improved TTL to MOS voltage level shifter circuit utilizes a totem pole output stage consisting of a pull-up junction transistor and a pull-down saturation junction transistor, an intermediate stage consisting essentially of a saturation junction transistor, an input stage consisting essentially of a diode and a saturation junction transistor, and current spike inhibit circuitry which consists essentially of a saturation junction transistor connected between the input stage and the base of the pull-down transistor. The current spike inhibit transistor, which turns on with the pull-down transistor, has a greater turnoff time than the pull-down transistor and consequently provides a relativley low impedance discharge path connected to the base of the pull-down transistor which allows the pull-down transistor to turn off before the pull-up transistor turns on. This helps insure against output current spikes that occur if the pull-up and pull-down transistors conduct simultaneously.

Growing community of inventors

Dallas, TX, United States of America

Paul R Schroeder