Koninklijke Philips Corporation N.v.

Nxp B.v.

Koninklijke Phillips Electronics N.v.

Snaptrack Incorporated

Paul R Marshall

Adrian G Spencer

Anthony D Sayers

Ian A Marsden

Richard Charles Burbidge

Christopher Brian Marshall

David Keith Roberts

A master-slave distributed communications network includes a master node, a plurality of slave nodes. Each slave node is configured to store an address of the next node for a message to be routed on an uplink to the master node, and when sending a data packet to the master node it appends the pre-stored address and forwards the data packet to the next node thus lengthening the data packet, as the data packet is progressed from the slave nodes to the master node. For a downlink message, the master node using a pre-stored routing table includes in the data packet the addresses of all the slave nodes on the selected route. As the data packet is progressed from slave node to slave node, the address of each slave node which has forwarded the data packet is deleted thus shortening the overall length of the data packet.

Wireless master-slave distributed communications network

A master-slave distributed communications network comprises a master node (), a plurality of slave nodes (to), and links (VL) operatively interconnecting the slave nodes and the master node in accordance with a routing plan. Each slave node has means for storing an address of the next node in the routing plan for a message to be routed on an uplink to the master node and when sending a data packet to the master node it appends the prestored address and forwards the data packet to the next node. If the next node is not the master node, it, in turn, adds the prestored address of the next following slave node to the data packet thus lengthening the data packet and re-transmits it, and so on until the data packet reaches the master node. For a downlink message, the master node () using a prestored routing table includes in the data packet the addresses of all the slave nodes on the selected route. As the data packet is progressed from slave node to slave node, the address of each slave node which has forwarded the data packet is deleted thus shortening the overall length of the data packet.

In communications systems such as telemetry systems in which a receiver () is periodically energised to receive transmissions from a central station, the receiver includes a power control means () for controlling the energisation of the receiver, a circuit () for detecting the presence of a carrier, which circuit () causes the power control means to de-energise the receiver () in the event of carrier not being detected, and a signal quality measuring stage () for determining if the demodulated signal is decodable, the stage () causing the power control means to de-energise the receiver () in the event of the signal quality not being acceptable.

Battery economizing in a communications system

A radio transceiver capable of transmitting and receiving on a common radio channel in a half duplex mode includes a direct conversion transmitter and a low IF receiver. A common signal generator () comprises a first and second frequency generator (). The first frequency generator generates a carrier frequency signal which is used by both the transmitter and receiver. During reception, the second frequency generator generates an offset signal at the low IF frequency which is mixed with the carrier frequency signal to form a down conversion signal. During transmission, modulation is applied either directly to the carrier frequency signal in one embodiment, or to the offset signal which is then mixed with the carrier frequency signal to form a modulated carrier frequency signal in another embodiment.

Direct conversion radio transceiver

A phase lock loop comprises a variable frequency oscillator (), a divider (), a phase comparator (), a gain control stage (), and a loop filter (). The frequency response of the loop is measured by superimposing a modulation at a number of different rates on the error signal generated by the phase comparator, and by measuring for each modulation rate the peak-to-peak variation of the loop control signal controlling the oscillator frequency. If, due to errors in component values, the frequency response deviates from its desired value, the loop gain is adjusted to bring the frequency response close to its desired value.

Phase-lock loops

A slave radio transceiver for use in a frequency hopping radio system synchronizes by receiving on a sequence of simultaneous combinations of radio channels until a paging message is received from a master transceiver, and may then revert to single channel frequency hopping operation. The slave's multi-channel receiver is sub-equipped to receive simultaneously on a only sub-set (PFPF) of the channels within its bandwidth, the received channels being selected by independent programming within the bandwidth. The channels received simultaneously may be selected to correspond to different degrees of misalignment between the master and slave.

Method and apparatus for synchronizing frequency hopping transceivers

A phase locked loop frequency (PLL) synthesizer in which the scaled output of a reference oscillator( ) is compared with the scaled output of a voltage controlled oscillator(VCO)( ) in a comparator( ) to provide an error voltage which is integrated to form a frequency control voltage for the VCO. When the VCO has stabilized, the PLL is interrupted by the opening of a switch( ) in the output circuit of the comparator( ) and de-energizing the reference oscillator( ), scalers( ) and the comparator( ). A capacitor( ) which has been charged by the frequency control voltage maintains the output frequency of the VCO. Periodically the de-energized stages are re-energized and the switch( ) is closed to restore the PLL thereby enabling the VCO( ) to stabilize again after which the cycle of operations is repeated. A technique is disclosed for avoiding a jump in the VCO frequency when the switch( ) is closed.

Low power phase locked loop frequency synthesizer

A method of powering-up a battery powered equipment by a phased activation of a function, for example the gain of a power amplifier ( ), to increase the current consumption in a manner which avoids an excessive transitory drop in the supply voltage from the battery ( ). Such a transitory drop may inhibit the powering-up operation and also may cause the battery to be exchanged prematurely because it appears that the battery is no longer usable. The phased activation of the function may be effected in a pre-planned phase sequence or by using a control loop monitoring the supply voltage.

Method of powering-up battery powered apparatus

A frequency generating circuit comprises a first, fine PLL frequency synthesiser circuit (FS ) which consumes a low current and is slow to settle, a second, coarse PLL frequency synthesiser circuit (FS ) which consumes a high current and is fast to settle, and a signal combining circuit ( ) for additively combining the outputs of the first and second frequency synthesiser circuits to provide a final output frequency. The first frequency synthesiser circuit is energised sufficiently in advance of the second frequency synthesiser circuit that both achieve lock substantially simultaneously. The overall current consumed is less than would be consumed if a single PLL frequency synthesiser is used to generate the final frequency.

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Redhill, United Kingdom

Paul R Marshall