Micro Linear Corporation

University of California

Signetics

Intel Corporation

Paul R Gray

Carlos A Laber

Mark L Stephens

David A Hodges

James L McCreary

Cheng-Chung Shih

Michael Armstrong

Joey Doernberg

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.

Circuit technique that sets transconductance

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit uses an active integrator. The integrator has a left-half plane pole. A feedback path is provided that includes a resistive impedance which comprises a MOS transistor operated in the triode region. The resistive impedance is adjustable for cancelling the pole. The feedback path also includes a capacitive impedance coupled in series with the resistive impedance.

Differential amplifier based integrator having a left-half plane pole

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2 Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mbps, and is built in a 1.5.mu./4 GHz BiCMOS technology.

Slimmer circuit technique

A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.

Self-calibrating analog to digital converter

This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.

Very high gain positive feedback CMOS transconductance amplifier

A flash ADC utilizes parallel weighted capacitive arrays and a resistor string to provide reference voltage intervals and an encoder for indicating the reference voltage interval wherein an input voltage lies. For an embodiment having N branches, the reference voltage intervals are subdivided into N sub-intervals and each succeeding clock cycle.

Flash A/D converter using capacitor arrays

An algorithmic analog-to-digital and digital-to-analog converter 10 combines the techniques of switched capacitor cyclic conversion by using first and second amplifiers 31, 32 with capacitors C.sub.1, C.sub.1 ', C.sub.2, C.sub.2 ', C.sub.3, C.sub.3 ', C.sub.4, C.sub.4 ', C.sub.5, C.sub.5 ' communicating with the inputs of said amplifiers 31, 32 and between the inputs and outputs of said amplifiers 31, 32, and the techniques of reference voltage refreshing. The performance of the converter 10 is capacitor ratio-independent. Because of the ratio-independent aspect, very small component values can be used, and as a result, the die area required for the circuitry can be quite small.

Ratio independent cyclic A/D and D/A conversion using a reciprocating

An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed. Resolution of the coder/decoder is increased by providing a reference voltage generator capable of supplying stepped increments of the reference voltage to the capacitor array during the comparison process.

Weighted capacitor analog/digital converting apparatus and method

A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.

Bridge drive circuit and method

An active filter employing a plurality of integrators which may be fabricated as a metal-oxide-semiconductor (MOS) integrated circuit is described. S-plane zeros are obtained without additional active devices when compared to prior art filters without such zeros. The zeros result from resistive coupling between the integrators. Resistance ratios and capacitance ratios primarily determine the filter's characteristics rather than the absolute value of these elements. This permits the filter to be readily fabricated with existing MOS technology.

LC Simulated filter with transmission zeros

A temperature compensated piezoresistive transducer includes a silicon body having a major top surface and an under surface. The body has generally parallel spaced first and second elongate slots formed therein extending through said top and under surfaces to define a center portion between said slots and first and second outer portions at the outward edge of the respective slots. The center portion is adapted to receive pressure to be measured. The body has an additional slot extending through the top and bottom surfaces and extending around the first, second and center portions to define the outer periphery of a transducer membrane with portions of the body remaining to integrally support the membrane. Plural piezoresistive elements having elongate and transverse dimensions are formed on the membrane. The elements are arrayed to receive compressive and tensile stress when pressure is applied.

Temperature compensated piezoresistive transducer

An array of binary weighed capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

An amplifier circuit and structure having high input impedance and having a return path for conducting amplifier DC leakage current. A common diode structure forms the return path and includes two diodes connected in series and connected in opposite conduction directions. The diode having a forward conduction direction which is in the opposite direction of the leakage current is provided with a reverse saturation current which is substantially greater than the leakage current of the amplifier. The amplifier is typically a P channel or N channel field effect transistor (FET) and the double diode structure is typically an NPN or PNP transistor.

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Orinda, CA, United States of America

Paul R Gray