Cisco Technology, Inc.

U.S. Philips Corporation

Coreoptics, Inc.

Paul Presslein

Theodor Kupfer

Markus Danninger

Claus Dorschky

Achim Herzberger

This invention relates to a receiver circuit which comprises an equalizer () and an error decorrelator (). The error decorrelator being configured for changing () the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols () within a stream of digital data () thereby obtaining selected symbols. The method further comprises exchanging () the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.

Modification of error statistics behind equalizer to improve inter-working with different FEC codes

A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device that initially receives the N bit digital data signal, and a sink device that receives the N bit digital data signal from the source device. The N bit digital data signal has a skew when received by the sink device. A skew detection circuit in the sink device detects the skew in the N bit digital data signal and generates a skew detection signal. A line supplies the skew detection signal to the source device. A compensation circuit in the source device receives the skew detection signal and compensates for the skew in the N bit digital data signal.

Method and apparatus for compensating for timing variances in digital data transmission channels

A demultiplexer for an isochronous multiplex signal is described which signal consists of isochronous sub-signals interleaved block by block. The demultiplexer comprises a read-write memory (MXA, MXB, MXC, MXD) as well as a read-write control (ST). The proposed circuit arrangement may be devised in a highly advantageous manner as an integrated circuit because it is has been considered that, for example, the manufacturers of gate arrays leave the user only the choice of using building blocks depicted in a catalogue. These building blocks constitute the function blocks (MXA to MXD) which are provided for partitioning an STM-16 signal into four sub-signals (STM4A, STM4B, STM4C, STM4D). The control signals for these function blocks (TL15:0, Z(3:0), T311, T622) are produced by a control circuit (ST) whose central module is a four-stage cyclic counter. The necessary control signals are derived from the count of the cyclic counter by means of addressable demultiplexers.

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Ebermannstadt, Germany

Paul Presslein