Broadcom Corporation

Qualcomm Incorporated

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Paul Penzes

Mark Norman Fullerton

Dipti Ranjan Pal

Ryan Michael Coutts

John S Walley

Mehdi Hatamian

David Anthony Kidd

Mehdi Saeidi

Mohamed Waleed Allam

Yi Lou

Ardavan Moassessi

Wai Kit Siu

Vafa James Rakshani

Ramaprasath Vilangudipitchai

Love Kothari

Rajat Mittal

Shih-Hsin Jason Hu

Tim Sippel

Alvin Lin

Hwisung Jung

Melika Roshandell

Ajat Hukkoo

Vasisht M Vadi

Ajit Kumar Vallabhaneni

Samy Shafik Tawfik Zaynoun

Ajay Vadakkepatt

Ankita Nayak

Shahin Solki

Albert Kumar

Arjang Shahriari

Mahdi Nabil

Ingyeom Kim

Wei Yi

Pranjal Srivastava

Koen Lampaert

A device that includes a first integrated device, a second integrated device configured to be electrically coupled to the first integrated device and an electrowetting device configured to be electrically coupled to the second integrated device. The electrowetting device is configured to redistribute heat across a back surface of the device by looping a liquid in the electrowetting device, along the back surface of the device.

Electronic device comprising an electrowetting device

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Adaptive clocking scheme

A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.

High-voltage tolerant level shifter using thin-oxide transistors and a middle-of-the-line (MOL) capacitor

In one embodiment, a temperature management system comprises a plurality of thermal sensors at different locations on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the thermal sensors, to fit a quadratic temperature model to the received temperature readings, and to estimate a hotspot temperature on the chip using the fitted quadratic temperature model.

Thermal sensor placement for hotspot interpolation

Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that the sensor circuit receives the endpoint's data signal and clock signal. The sensor circuit introduces skew between the data signal and the clock signal by delaying the data signal more than the clock signal, and compares skewed data signals to determine if an error occurs because of the induced skew. By delaying the data signal with different delay amounts and monitoring what delays cause errors, an amount of timing slack in the data signal and clock signal (e.g., margin to criticality) is measured during operation of the chip for relevant circuitry to the system implemented on the chip, compared to test circuitry operating while the chip is in a test mode.

Estimating timing slack with an endpoint criticality sensor circuit

Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

Power-density-based clock cell spacing

Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling

Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Dynamic clock and voltage scaling with low-latency switching

A method of setting a supply voltage in a device is disclosed. The method includes receiving a first plurality of inputs from a plurality of sensors that are representative of a gate delay of a signal path on the device, and receiving a second plurality of inputs from a plurality of temperature sensors. The method further includes estimating a plurality of interconnect delays for the signal path based on the second plurality of inputs, and determining the supply voltage for the signal path based on the first plurality of inputs and the plurality of interconnect delays.

Adaptive voltage scaling using analytical models for interconnect delay

A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

High-speed flip-flop with robust scan-in path hold time

A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Reset scheme for scan chains with asynchronous reset signals

Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are 'SET' flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are 'RESET' flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Systems and methods for setting logic to a desired leakage state

Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Systems and methods for distributing an aging burden among processor cores

A duty cycle adjustment apparatus includes a duty cycle adjustment determination module configured to determine an adjustment to a duty cycle of a clock signal, and includes a clock delay module configured to receive the clock signal, to delay the clock signal through first and second delay stage modules (with a first and a second plurality of delay paths, respectively) based on the duty cycle adjustment determined by the duty cycle adjustment determination module, and to output the delayed clock signal. The second plurality of delay paths have a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths. The apparatus further includes a duty cycle adjustment module configured to receive the clock signal and the delayed clock signal, to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal.

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Irvine, CA, United States of America

Paul Penzes