Oracle International Corporation

Sun Microsystems, Inc.

Western Digital Technologies, Inc.

Oracle America, Inc.

Paul N Loewenstein

Erik E Hagersten

Robert Paul Masleid

Satyanarayana Nishtala

William C Van Loo

Zahir Ebrahim

Stephen Phillips

Robert Cypher

Kevin B Normoyle

Ali Vahidsafa

Thomas M Wicki

Zoran Radovic

Kathirgamar Aingaran

Louis F Coffin, Iii

David Smentek

Damien Walker

David Dice

Mark S Moir

Sumti Jairath

Mark Luttrell

John Johnson

Josephus Ebergen

Mark Sean Moir

Ramaswamy Sivaramakrishnan

Monica C Wong-Chan

Don Draper

Matthew Cohen

Thirumalai Swamy Suresh

Serena Wing Yee Leung

Priyambada Mitra

Andrew Brock

Venkat Krishnaswamy

Shailender Chaudhry

Paul Joseph Jordan

Dejan Vucinic

William Havinden Bridge, Jr

Sorin Iacobovici

Jurgen M Schulz

Anders Landin

Marjan Radi

Robert C Zak, Jr

Chaiyasit Manovit

William A Nesheim

Connie Wai Mun Cheung

Håkan E Zeffer

Manling Yang

Jaco Hofmann

Huynh Tu Dang

Louis F Coffin Iii

Sue K Lee

John R Catenzaro

Basant Vinaik

Nicholas E Aneshansley

Mark A Luttrell

John G Johnson

William H Bridge

Stephen E Phillips

Aingaran Kathirgamar

David Richard Smentek

A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.

Fault tolerance and coherence for shared memory

On-die functional blocks may use multiple communication networks to send requests and receive responses. For example, a first functional block may send a request via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

Multiple on-die communication networks

A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

Fault-tolerant cache coherence over a lossy network

The disclosed embodiments provide a memory system that provides error detection and correction. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C&#x2212;M&#x2212;1 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and M inner check bit columns that collectively include MR inner check bits. These inner check bits are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is associated with a different pin in a memory module interface, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors that arise during the transmission. During operation, the system transmits a block of data from the memory. Next, the system uses an error-detection circuit to examine the block of data, and determine whether an error has occurred during the transmission based on the examination.

Robust pin-correcting error-correcting code

A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.

Reducing cache coherence directory bandwidth by aggregating victimization requests

A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no 'dirty' data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system.

Memory sharing across distributed nodes

A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

Inter-processor bus link and switch chip failure recovery

Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.

Load-monitor mwait

Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as 'shared cache lines.' A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.

Memory corruption detection support for distributed shared memory applications

A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

Cache probe request to optimize I/O directed caching

A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, a special data value is used to indicate that data in a mirrored memory location is not valid. This enables a sharer node to know when to obtain valid data from a home node. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no 'dirty' data is transferred between sharer nodes. Consequently, the failure of one node will not cause the failure of another node or the failure of the entire system.

An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

Digital encoding of parallel busses to suppress simultaneous switching output noise

Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

Codec to reduce simultaneously switching outputs

Growing community of inventors

Palo Alto, CA, United States of America

Paul N Loewenstein