Imagination Technologies Limited

Nordic Semiconductor Asa

Paul Murrin

Adrian John Anderson

Mohammed El-Hajjar

Gareth J Davies

Filipe Carvalho

Mohammed Alloulah

Alamo Spaargaren

Bastien Beauvois

Nitzan Tzifroni

Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Tile based interleaving and de-interleaving for digital signal processing

Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.

Dynamic scaling of channel state information

A gaussian frequency shift keying (GFSK) detector comprising a multi-symbol detector; at least three Viterbi decoders, and a timing adjustment module. The multi-symbol detector receives a series of samples representing a received GFSK modulated signal which comprises at least three samples per symbol; and generates, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, at least three sets of soft decisions values, each set of soft decision values indicating the probability that the N-symbol sequence of samples is each possible N-symbol pattern based on a different one of the at least three samples of a symbol being a centre sample of the symbol. Each Viterbi decoder generates, for each N-symbol sequence, a path metric for each possible N-symbol pattern from a different set of soft decision values according to a Viterbi decoding algorithm. The timing adjustment module generates a timing adjustment signal based on the path metrics generated by the Viterbi decoders to adjust the sample timing.

Systems and methods for adjusting the sample timing of a GFSK modulated signal

A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

GFSK detector

A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.

Controlling register bank access between program and dedicated processors in a processing system

A logging unit is used to log entries for events in a computer system. Each entry includes an n-bit timestamp field and a payload. The payload includes information about the event and the timestamp field includes the n least significant bits of an N-bit timestamp for the event, where N&#x3e;n. If the n least significant bits of the timestamp have wrapped compared to the corresponding n bits of the timestamp of the preceding entry then a timing entry is logged which includes other bits of the timestamp. Therefore, an N-bit timestamp can be determined for an event, but only the n least significant bits of the timestamp are stored in the timestamp field of an entry for the event. Therefore, the time flow of events in the store is better maintained (by having a larger timestamp) without increasing the number of bits (n) in the timestamp field of each entry.

Logging events with timestamps

Methods and OFDM receivers for decoding an OFDM signal include estimating a channel impulse response from a pilot-dense symbol of the OFDM signal for each of a plurality of potential FFT window positions; determining a noise floor of each of the channel impulse responses; selecting the potential window position corresponding to the channel impulse response with the lowest noise floor as an optimum FFT window position; and decoding symbols of the OFDM signal using the optimum FFT window position.

Minimizing inter-symbol interference in OFDM signals

Distortion caused by spurious components in a determined channel impulse response (CIR) is reduced. In an OFDM (orthogonal frequency-division multiplexing) system pilot signals are applied to different subcarriers of different symbols in accordance with a pilot transmission scheme. Channel estimates are determined by time-interpolation for some of the data slots of the received signal which do not already include a pilot signal. For each of a sequence of symbols, a respective Inverse Fast Fourier Transform is performed on the pilot signals and interpolated channel estimates in the data slots of that symbol, thereby determining a sequence of estimated CIRs for the sequence of symbols. Spurious channel components will vary across the sequence of estimated CIRs, whereas the true channel peaks will tend not to significantly vary across the sequence of estimated CIRs. Therefore the sequence of estimated CIRs can be filtered (e.g. with a low-pass filter) to attenuate the spurious components, thereby determining a CIR for the signal for which the distortion caused by the spurious components is reduced.

Determining signal channel impulse response using subcarrier pilot signals

A non-data-aided method of calculating an estimate of the sampling frequency offset (SFO) in a digital receiver involves performing a plurality of correlations between two identical sized groups of samples within a received signal where the spacing of the groups is varied for each correlation. In various examples the number of samples in the groups is also varied. For larger symbols, the group of samples may comprise approximately the same number of samples as the guard interval in a symbol and for smaller symbols, the group of samples may comprise approximately the same number of samples as an entire symbol. An estimate of the SFO is determined by identifying the largest correlation result obtained from all the correlations performed. The largest correlation result indicates the largest correlation.

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Chepstow, United Kingdom

Paul Murrin