International Business Machines Corporation

Mentor Graphics Corporation

Paul Michael Steinmetz

Anthony Correale, Jr

Benjamin Bowers

Matthew Wayne Baker

Irfan Rashid

Michael B Mitchell

James Norris Dieffenderfer

Thomas Philip Speier

Praveen Karandikar

Kenichi Tsuchiya

Nicole Marie Arnold

Bechara Fouad Boury

Anthony L Polomik

Embodiments that design integrated circuits using a 1&#xd7;N compiler in a closed-loop 1&#xd7;N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1&#xd7;N building blocks. The embodiments may alter elements of the 1&#xd7;N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1&#xd7;N building block elements.

Compiler for closed-loop 1&#xd7;N VLSI design

A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Computing device with asynchronous auxiliary execution unit

Compiler for closed-loop 1xN VLSI design

Embodiments that create parent-child relationships for reuse of 1&#xd7;N building blocks in a closed-loop 1&#xd7;N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1&#xd7;N building block into the representation, and creating an association between the first 1&#xd7;N building block and a second 1&#xd7;N building block. The association enables the first 1&#xd7;N building block to inherit alterations of attributes of the second 1&#xd7;N building block and enables unique alterations of attributes of the first 1&#xd7;N building block which differ from the second 1&#xd7;N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1&#xd7;N building blocks, an attribute creator that creates a set of attributes and enables one of the 1&#xd7;N building blocks to inherit parent attributes and comprise child attributes.

Uniquification and parent-child constructs for 1xN VLSI design

Embodiments that make DFM alterations to cells of 1&#xd7;N building blocks via a closed-loop 1&#xd7;N compiler are disclosed. Some embodiments comprise using a 1&#xd7;N compiler to detect a relationship between two adjacent cells of a 1&#xd7;N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1&#xd7;N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Integrated design for manufacturing for 1&#xd7;N VLSI design

Embodiments that reassemble hierarchical representations in a closed-loop 1&#xd7;N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1&#xd7;N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1&#xd7;N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1&#xd7;N compiler and a reassembler. The 1&#xd7;N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1&#xd7;N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1&#xd7;N building block that reflects alteration of elements to the flat netlist.

Hierarchy reassembler for 1&#xd7;N VLSI design

Embodiments that design integrated circuits using a closed loop 1&#xd7;N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1&#xd7;N building blocks. The embodiments may alter elements of the 1&#xd7;N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1&#xd7;N compiler. The viewer may generate displays of behavioral representations of 1&#xd7;N building blocks, with the behavioral representations comprising RTL definitions. The 1&#xd7;N compiler may create physical design representations of the 1&#xd7;N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.

Closed-loop 1&#xd7;N VLSI design system

Embodiments that route 1&#xd7;N building blocks using higher-level wiring information for a 1&#xd7;N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1&#xd7;N building block, determining intra-1&#xd7;N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1&#xd7;N wires of the 1&#xd7;N building block that avoid the intra-1&#xd7;N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1&#xd7;N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1&#xd7;N wiring for the 1&#xd7;N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1&#xd7;N wiring for the 1&#xd7;N building block.

Top level hierarchy wiring via 1&#xd7;N compiler

A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed.

Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank

Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Promoting a line from shared to exclusive in a cache

Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache

A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.

Growing community of inventors

Holly Springs, NC, United States of America

Paul Michael Steinmetz