International Business Machines Corporation

Purdue Research Foundation

Paul Michael Solomon

Guy M Cohen

Kevin K Chan

Yulong Li

Christian Lavoie

Dennis Merton Newns

Effendi Leobandung

Matthew Warren Copel

Seyoung Kim

Min Yang

Erin C Jones

Siyuranga O Koswatta

Jack Oon Chu

Ahmet Serkan Ozcan

Meikei Ieong

Kathryn Wilder Guarini

Tak H Ning

Cyril Cabral, Jr

Xiao Lin Sun

Fenton Read McFeely

Glenn John Martyna

Bruce Gordon Elmegreen

Jin-Ping Han

Jeng-Bang Yau

Zhen Zhang

Hussein Ibrahim Hanafi

Chun-Chen Yeh

Tayfun Gokmen

Ronnen Andrew Roy

Kam-Leung Lee

John Bruley

Alexander Reznicek

Martin Michael Frank

Ramachandran Muralidhar

Hon-Sum Philip Wong

Chun-Yung Sung

Victor Chan

David James Frank

Yu Luo

Wooram Lee

Rajesh Rengarajan

Bin Yang

Thomas M Shaw

Jason Scott Orcutt

Zhibin Ren

Jin Ping Han

Bruce Bennett Doris

Chun-chen Yeh

Shu-Jen Han

Ying Di Zhang

Isaac Lauer

Joshua T Smith

Amlan Majumdar

Supratik Guha

Wilfried Haensch

Eduard Albert Cartier

Damon B Farmer

Sufi Zafar

Xiao Hu Liu

Talia S Gershon

Steven John Koester

John Albrecht Ott

Jerry M Woodall

Jeremy H Burroughes

Steven Lorenz Wright

Aaron Daniel Franklin

Sandip Tiwari

Xiaoyan Shao

Christopher Peter D'Emic

John Jacob Yurkas

Michael Joseph Rooks

Huiling Shang

Rodney T Hodgson

Devendra K Sadana

Vijay Narayanan

Ali Afzali-Ardakani

Kuen-Ting Shiu

Kisik Choi

Christos Dimitrios Dimitrakopoulos

Qiqing Christine Ouyang

Jane M Shaw

Rajarao Jammy

Masatoshi Ishii

Richard Quimby Williams

Phaedon Avouris

Heike E Riel

Philip Joseph Oldiges

Geoffrey W Burr

John Rozen

Cherie Renee Kagan

Yanning Sun

Siegfried Friedrich Karg

Xin Zhang

Jia Chen

Roy Arthur Carruthers

James M Harper

Walter Heinrich Riess

Siegfried K Wiedmann

Pritish Narayanan

Xiaodong Cui

A memory device that includes a plurality of memory cells including sample capacitors and hold capacitors in an array geometry; a readout transistor in electrical communication with the sample capacitors and hold capacitors; and a peripheral amplifier. The memory device further includes an analog multiplexer that controls digital and analog signal to the array of memory cells to provide for random access of the memory cells. The read transistor provides a single source follower transistor for each memory cell of the plurality of memory cells to the peripheral amplifier.

Fractal analog random access memory

Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.

Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks

A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

Field effect transistor with controllable resistance

A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Circuit methodology for highly linear and symmetric resistive processing unit

A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Selective application of multiple pulse durations to crossbar arrays

A substrate's embedded substrate contact electrode forms a reference voltage point. A gate insulator is spaced outwardly from the substrate and has an exposed outer surface configured for contact with a fluid analyte. A device region is intermediate the substrate and the gate insulator; source and drain regions are adjacent the device region; and a field insulator is spaced outwardly of the drain region, the source region, and the substrate away from the device region. The gate insulator and the field oxide are formed of different materials having different chemical sensitivities to the fluid analyte. The field insulator is coupled to the substrate through the field insulator capacitance. The gate insulator capacitance is much smaller than the field insulator capacitance. The embedded substrate contact electrode can be connected to a separate voltage so that the electrical potential between the substrate and the source region can be controlled.

Ion sensitive field effect transistor (FET) with back-gate coupled reference electrode

An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

Two-terminal non-volatile memory cell for decoupled read and write operations

Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

Analog circuit for softmax function

Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Aggregate adjustments in a cross bar neural network

Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example method includes setting a state of each single bit counter from a set of single bit counters in the crosspoint device, the states of the single bit counters representing the weight to be stored at the crosspoint device. The method further includes adjusting electrical conductance of a resistor device of the crosspoint device. The resistor device includes a set of resistive circuits, each resistive circuit associated with a respective single bit counter from the set of single bit counters, the electrical conductance adjusted by activating or deactivating each resistive circuit according to a state of the associated single bit counter.

Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.

Capacitor based resistive processing unit with symmetric weight update

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West Chester, NY, United States of America

Paul Michael Solomon