National Semiconductor Corporation

Burr-brown Corporation

Paul Michael Henry

Gregory J Smith

David J Kunst

John Wendell Oglesbee

Steven A Martinez

Stephen R Burnham

Wade Leitner

A system and method is disclosed for providing an offset voltage minimization circuit for an amplifier circuit. The present invention comprises a flip flop zero amplifier circuit that is capable of operating in a first configuration during a first period of time to obtain a first value of offset voltage. The flip flop zero amplifier circuit is also capable of operating in a second configuration during a second period of time to obtain a second value of offset voltage that has a polarity that is opposite to that of the first value of offset voltage. The two values of offset voltage are then averaged to obtain an average value of offset voltage that is approximately zero volts. The invention may be advantageously employed in a switching power supply circuit.

System and method for providing an offset voltage minimization circuit

A multi-stage amplifier circuit that is arranged to minimize offset related errors in a reference circuit. The first stage circuit includes an array of amplifier circuits that receive feedback signals. The outputs of the first stage amplifier circuits are coupled together to a common node. The second stage circuit is also coupled to the common node, and arranged to drive a feedback circuit to generate the feedback signals. In one example, the feedback circuit includes a band-gap core. The second stage circuit can be arranged as part of a low-drop out (LDO) regulator. Each of the amplifier circuits in the first stage can be nulled in response to null control signals from a null control logic circuit. The overall offset in the resulting reference circuit is reduced by the selective nulling of the arrayed amplifiers in the first stage circuit.

Nulled error amplifier

A reference circuit includes a band-gap core, two current sources, and an amplifier circuit that are arranged in cooperation. The band-gap core circuit is biased by current that is supplied from a local power supply via the first current source. The second current source shunts the excess away from the band-gap core circuit in response to a control signal. The control signal is provided by the amplifier circuit, which is arranged to monitor the signals in the band-gap core circuit. The feedback loop that is formed with the amplifier circuit is compensated with a capacitor that is not referenced to the local power supply. The first current source can be further improved by cascading. The reference circuit has excellent characteristics for use in switching applications, where the local supply is perturbed by fast switching transients.

Band-gap reference

A transient rejecting system for protecting the state of a memory is described. The transient rejecting system includes a signal transfer circuit and a charge storage circuit coupled to at least one pin of a circuit. The signal transfer circuit receives a supply signal and determines when a transient event occurs. When a transient event occurs, the charge storage circuit provides a signal to the pin of the circuit maintaining the state of the memory prior to the transient. During normal operation, the charge storage circuit is charged, and the supply signal is provided to the pin of the memory circuit. P-channel FETs are used in the signal transfer circuit and allow for low voltage operation of the transient rejecting system.

Transient rejecting circuit

To generate a signal delay, a current source, a reference voltage generator and a comparator are turned on. Once turned on, the current source raises the voltage across an initially discharged capacitor to a minimum required threshold. The comparator then compares the capacitor voltage to the reference voltage thereby to generate the delay signal. Thereafter, the current source, the reference voltage generator and substantial blocks of circuitry in the comparator are switched off to reduce quiescent power consumption.

Micropower delay circuit

A comparator circuit performs at least three compare operations, wherein in each compare operation the comparator compares two of at least three reference voltages to one another and provides a signal to indicate which of the two reference voltages is greater. A decode logic circuit in response to the signals provided by the comparator circuit in the at least three compare operations selects the median reference voltage from among the at least three reference voltages, and causes a multiplexer to transfer the median reference voltage to an output terminal of the mux.

Median reference voltage selection circuit

Current-level monitoring circuitry incorporating a full-time coarse monitor and a part-time fine monitor and capable of generating control signals when the current-level being monitored reaches certain predetermined thresholds. In its preferred embodiment the invention is incorporated into battery-protection circuitry, guarding against both excess charging currents and excess discharging currents. A key concept of the invention is a hierarchical monitoring system incorporating a full-time coarse monitor that activates the fine monitor only when the battery current level enters a certain range and then deactivates it once the level falls out of that range again. Should the current level continue to rise up to the threshold of unsafe battery current, the fine monitor will disconnect the battery. In the preferred embodiment of the invention, the fine monitor operates by comparing, with a predetermined reference voltage, the voltage drop across a fine sensing resistor through which battery current is directed. The fine sensing resistor may be a precision resistor or it may be the same resistance used by the coarse monitor. The reference voltage is established in a way that permits a differing disconnect threshold to be set depending on the battery current polarity and in such a way that it changes with temperature so as to largely offset the temperature dependence of the sensing resistors. The present invention utilizes a single fine comparator for monitoring both battery-charge and battery-discharge, thereby providing high accuracy without the need for an additional fine comparator with its high space and power demands.

Current-level monitor with hierarchical precision

A power switch includes two power FETs connected back-to-back in series at a common source node and a common gate node and a resistor connected between the common source node and the common gate node. The switch further includes a current source and a single-control switch connected to the current source and to the gate node for switching the current source to the gates of the two power FETs.

Method and apparatus for connecting and disconnecting a power field

Circuitry and method for compensating for the junction leakage current of a reverse-biased semiconductor device. Compensation is effected by trimming the leakage of a compensating device at a high temperature in order to accurately compensate the leakage current over a broad range of temperatures. Potential applications include reduction of the input bias current of an amplifier or differential amplifier.

Circuit and method for semiconductor leakage current compensation

A band-gap voltage reference circuit which incorporates a band-gap differential amplifier supplied with constant, temperature-independent current, a high gain differential-to-single-ended converter, temperature-compensated negative feedback means and a common source of biasing to serve as a device to provide an output reference voltage so that the output reference voltage is precise and independent of variations in temperature, loading and power supply voltage. An improved amplifier is also disclosed.

Precision band-gap voltage reference circuit

A band gap voltage reference circuit includes first and second NPN transistors coupled as differential pair having ratioed emitters, to produce an offset voltage, and third and fourth emitter-coupled PNP transistors connected as a current mirror to function as load devices for the first and second transistors. The emitters of the third and fourth transistors are coupled to a current source and also to a fifth PNP emitter follower transistor which drives the base of a sixth emitter follower transistor connected to the collector of a seventh transistor, the emitter of which is connected to a series string including first and second resistors. The emitter of the seventh transistor is coupled to the base of the first transistor and the junction between the first and second resistors is coupled to the base of the second transistor. The emitter of the sixth transistor is coupled to series connected third and fourth resistors, the junction of which is coupled to the base of the seventh transistor. The ratio of the first and second resistors is adjusted to cause a band gap voltage produced on the base of the seventh transistor to have a very low temperature coefficient. The third and fourth resistors are ratioed to produce an output voltage at the emitter of the sixth transistor which is scaled up from the band gap voltage.

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Tucson, AZ, United States of America

Paul Michael Henry