Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Paul Michael Guglielmi

Samuel Hammond Duncan

Craig Durand Keefer

Ricky C Hetherington

Alan Kotok

Glenn Arthur Herdeg

Thomas Adam McLaughlin

Maurice Bennet Steinman

David A Gross

Ronald J Melanson

Patrick Sullivan

Dale H Leuthold

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity, which minimizes the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Performance optimization and system bus duty cycle reduction by I/O

Method and apparatus for providing DMA transfers between devices coupled

Method and apparatus providing DMA transfers between devices coupled to

Latch circuit and method which permit two-phase latches and flip-flops to be intermixed in a system having level sensitive scanning without critical clock requirements. The circuit includes a master latch having a normal data input and a scan data input, and a slave latch connected to the master latch. A differential pair of clock signals is applied to the latches in a complementary manner during a normal mode of operation to load data from the normal data input to the master latch and to transfer the normal data from the master latch to the slave latch, and two separate low frequency non-overlapping scan clock phases are applied to the latches during a level sensitive scanning mode to load data from the scan data input to the master latch and to transfer the scan data from the master latch to the slave latch.

Latch circuit and method with complementary clocking and level sensitive

A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner. In addition, the chip includes circuitry that generates the control signals, in response to the latched control signals, with the correct timing for controlling the random access memory, obviating the necessity of the system designer designing a system including the chip having to design off-chip control circuitry with the required timing.

Self-timed random access memory chip

A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity. Logic in both the processor and the memory unit is initialized to acount for the words being transferred such that each word selected is stored in the proper buffer.

Memory control system for transferring selected words in a multiple

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Westboro, MA, United States of America

Paul Michael Guglielmi