Altera Corporation

Silicon Tailor Limited

Superfastfpga Limited

Paul Metzgen

Dominic James Nancekievill

Martin Langhammer

Steven Perry

Andrew Martyn Draper

Roger May

Leon Zheng

Neil Kenneth Thorne

William Hwang

Volker Mauer

Nitin Prasad

Kulwinder Singh Dhanoa

Kerry S Veenstra

Gregory W Starr

Jeffrey Orion Pritchard

Kumara Tharmalingam

Aaron Ferrucci

Tracy Miranda

A circuit having multiple inputs and multiple outputs the circuit being for switching signals received at any of the inputs to any of the outputs, the circuit comprising: a first switch matrix, the first switch matrix being capable of directing signals received at the inputs of the circuit to multiple first intermediate ports; a second switch matrix, the second switch matrix being capable of directing signals received at multiple second intermediate ports to multiple third intermediate ports, the number of the second intermediate ports being less than the number of the inputs of the circuit; one or more primary bypass links, each primary bypass link being capable of coupling one or more of the first intermediate ports to a respective one or more of the outputs of the circuit independently of the second switch matrix; a first redirection layer, the first redirection layer being capable of, for each first intermediate port, directing a signal received at that first intermediate port to a primary bypass link or to a second intermediate port; and a second redirection layer, the second redirection layer being capable of directing signals received at each of the primary bypass links to a respective one or more outputs of the circuit, and directing signals received at each of the third intermediate ports to a respective one or more outputs of the circuit.

Interconnect circuit

A logic circuit comprising: inputs for receiving multiple n-bit numbers, n being greater than one; and an adder capable of receiving m n-bit numbers, m being greater than one, and forming an output representing the sum of those numbers, the adder having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the numbers to an operation in a respective one of the single-bit stages, the single-bit stages being such that the adder has insufficient capacity to add all possible combinations of bits in a respective bit position of m n-bit numbers; the addition circuit being configured to add the multiple n-bit numbers by: in the adder, adding a first one of the n-bit numbers to a value corresponding to a set of non-consecutive bits of another of the n-bit numbers to form a first intermediate value; adding the first intermediate value to a value corresponding to the bits of the said other of the n-bit numbers other than those in the said set to form a sum; and outputting the sum.

Determining sums using logic circuits

A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

Pipelined configurable processor

A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.

Software-to-hardware compiler with symbol set inference analysis

Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.

Saturation and rounding in multiply-accumulate blocks

An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, obtains a result of the arithmetic operation and that transmits the result to a result register. The arithmetic logic unit includes a signal propagation path that includes no greater than two routing paths that connect non-immediately adjacent logic elements.

Arithmetic logic unit

A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.

Software-to-hardware compiler

Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.

Methods and apparatus for implementing a saturating multiplier

Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.

Embedded processor with dual-port SRAM for programmable logic

Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are included in the loop instruction. When a processor executes a loop instruction, it decodes the instruction, identifies the modifier register, and accesses the register value to determine if the processor will jump back based on the memory address information. The loop execution can incur no clock cycle penalties.

Loop instruction execution using a register identifier

In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.

Peak windowing for crest factor reduction

Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.

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London, United Kingdom

Paul Metzgen