National Semiconductor Corporation

Paul McKay Moore

Kevin Carl Brown

Richard Luttrell

Rashid Bashir

The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.

Pixel array for LC silicon light valve featuring pixels with overlapping edges

A pixel cell for a silicon LC light valve features a plurality of transparent electrically conducting pixel electrodes formed over a grounded reflective metal backplane. Dielectric material intervenes between the transparent electrodes and the grounded reflective backplane. This dielectric material, alone or in combination with the transparent electrode, creates a reflectance enhancing coating generating constructive interference of light reflected by the underlying backplane. The dielectric material also serves as the dielectric of an additional capacitive component having the active electrode and the grounded reflective metal backplane as plates. This architecture enhances the storage capacitance of the pixel cell, lowering sensitivity of the pixel to current leakage and reducing the pixel cell surface area. This pixel architecture also reduces the appearance of dark lines attributable to absorption of light in inter-pixel regions.

Pixel cell for silicon LC light valve having enhanced storage capacitance

A light absorbing thin film stack is placed in an upper interconnect level of a pixel cell of an LCD light valve to prevent transmission of light from the small gap between adjacent pixel electrodes into the silicon substrate. The light absorbing thin film stack includes a surface layer combination formed over a highly absorbing backstopping layer. Incident light is absorbed by the backstopping layer. Light reflected by the surface layer combination and/or the backstopping layer is extinguished by destructive interference. This destructive interference is generated by a change in the phase angle caused by the differing optical properties of the various layers of the light absorbing thin film stack.

Light absorbing thin film stack in a light valve structure

A receiver receives a signal transmitted by a time-division multi-access method that divides one frame into a plurality of communication slots in conducting communication. In this receiver, a detection circuit detects whether a received RF signal is stronger than a predetermined level. The received RF signal is demodulated by a demodulation circuit. An oscillation circuit generates a clock that is used to decode the data obtained by demodulation. The data obtained by demodulation is stored in a memory in synchronism with a clock reproduced from the received signal, and is then retrieved from the memory in synchronism with the clock generated by the oscillation circuit. This eliminates jitters. After jitter elimination, the data is decoded by a processing circuit. The writing/reading operation against the memory is initialized in accordance with a result output from the detection circuit.

A pixel cell array for a silicon light valve positions a reflective metal surface underneath inter-pixel regions. This underlying reflective metal surface reflects incident light, thereby preventing absorption of light in inter-pixel regions that can disturb charge stored in underlying capacitors or cause dark lines to appear between electrodes. The underlying reflective metal surface can be formed as a plurality of discrete, floating, electrically-isolated structures. Alternatively, the underlying reflective metal surface can formed as a plurality of discrete structures linked to adjacent pixel electrodes through via structures. The underlying reflective metal surface can also be designed as a continuous grid including a contact for receiving an applied bias.

Pixel array for silicon LC light valve featuring reflective metal surface underlying inter-pixel regions

A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) CMP of dielectric layer underlying the metal following SOG planarization; 2) CMP of dielectric layer underlying the metal following formation of vias; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes. First, the REC coats the freshly deposited metal layer immediately following deposition, preserving the metal in its highly reflective state. Second, the REC generates constructive interference of light reflected by the metal layer. This constructive interference can generate reflectivity greater than that of the bare metal surface.

Silicon interconnect passivation and metallization process optimized to maximize reflectance

A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes. First, the REC coats the freshly deposited metal layer immediately following deposition, preserving the metal in its highly reflective state. Second, the REC generates constructive interference of light reflected by the metal layer. This constructive interference can generate reflectivity greater than that of the bare metal surface.

Interconnect passivation and metallization process optimized to maximize reflectance

Applying layers of dielectric material to a reflective conductive surface of an integrated circuit, increases the reflectance of the surface. The layers of dielectric material alternate between high and low indices of refraction. To enable incident light waves to undergo a uniform phase change as the waves pass between the dielectric materials, the thickness of each of the layers of dielectric material is established such that each of the layers of dielectric material have a substantially equal optical thickness. As a result, when he dielectric layers reflect incident light waves, the reflected light waves constructively interfere to increase the reflectance of the surface of the integrated circuit.

Reflectance enhancing thin film stack in which pairs of dielectric

Reflectance of a silicon light valve is preserved by eliminating bowing in the wafer and by retaining the pad etch photoresist mask on the wafer until insertion of LC material. Wafer bowing is eliminated by performing backside etching to remove polysilicon and oxide accumulated during previous polysilicon deposition steps. The pad etch photoresist mask serves as passivation during wafer transport and testing before liquid crystal material is inserted. The pad etch photoresist mask is removed during the cleaning step that is required prior to insertion of LC material. Elimination of the redundant pad etch photoresist mask stripping step spares the metal electrodes of the precursor light valve structure from roughness and loss of reflectance that would be caused by the extra cleaning step.

Process flow optimized to protect reflectance of silicon light valve

A liquid crystal transducer pixel cell includes support pillars separating a top and bottom plate of the cell. During the process for forming the pixel cell, the support pillars are formed prior to formation of the pixel electrode. This process flow obviates the need for depositing a thick dielectric layer on top of the pixel electrode. This process flow also prevents exposure of the surface of the pixel electrode to etching during subsequent processing, preserving the reflectance of the pixel cell electrode. Finally, the process flow in accordance with the present invention eliminates the creation of keyhole voids within the support pillars by forming the support pillars over a flat upper level intermetal dielectric rather than over narrow trenches formed in the pixel electrode layer.

Thin liquid crystal transducer pixel cell having self-aligned support

An array of pixels in a liquid crystal silicon light valve are fabricated with a minimum of surface topology by forming raised dielectric spacer walls on an underlying array support surface prior to the deposition of the metal pixel electrode layer. Deposition of the metal pixel electrode layer, followed by chemical-mechanical polishing to stop on the top of the spacer walls, produces an electrode surface that is flush with the tops of the dielectric spacer walls. This resulting planarity in the surface of the pixel cell array minimizes surface topology exhibited by the array, maximizing reflectance of the light valve.

Polished self-aligned pixel for a liquid crystal silicon light valve

An array of pixel cells for a liquid crystal light value includes support pillars separating the array surface from a translucent top plate. During fabrication, a series of raised intersecting spacer walls having sides and a top surface are first formed by etching a thick oxide layer to stop on a nitride layer. Exposed nitride etch-stop layer is then removed, and electrode liner, metal electrode, and passivation layers are formed over the entire structure, including the sides and top surface of the spacer walls. Photoresist is then spun, hardened, and etched to expose the passivation formed over the tops of the spacer walls. The exposed passivation layer, and pixel liner and metal electrode material underneath the exposed passivation layer at the margins of the spacer walls are then etched. A photoresist mask is patterned to cover points of intersection of the spacer walls, and unmasked lengths of spacer walls are etched to stop on the nitride etch-stop layer. Stripping the photoresist mask reveals raised support pillars at the corners of the pixels, with pixel electrodes electrically isolated from each other by inter-pixel isolation strips formed by the nitride bases of the former spacer walls. Careful control of the prior etching along the spacer wall margins creates an array surface having electrodes substantially planar with the inter-pixel isolation strips.

Growing community of inventors

San Bruno, CA, United States of America

Paul McKay Moore